---

yaml
---
r: 307412
b: refs/heads/master
c: ecb9785
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: fa193ff7999a7c1cdd1723f1cbc4a108540ca478
+refs/heads/master: ecb978515c88183b111b8994acd6b572b1361a72

trunk/drivers/gpu/drm/i915/intel_hdmi.c

@@ -153,6 +153,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 	val |= intel_infoframe_index(frame);
 
+	val &= ~intel_infoframe_enable(frame);
 	val |= VIDEO_DIP_ENABLE;
 
 	I915_WRITE(VIDEO_DIP_CTL, val);
@@ -185,6 +186,13 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 	val |= intel_infoframe_index(frame);
 
+	/* The DIP control register spec says that we need to update the AVI
+	 * infoframe without clearing its enable bit */
+	if (frame->type == DIP_TYPE_AVI)
+		val |= VIDEO_DIP_ENABLE_AVI;
+	else
+		val &= ~intel_infoframe_enable(frame);
+
 	val |= VIDEO_DIP_ENABLE;
 
 	I915_WRITE(reg, val);
@@ -217,6 +225,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 	val |= intel_infoframe_index(frame);
 
+	val &= ~intel_infoframe_enable(frame);
 	val |= VIDEO_DIP_ENABLE;
 
 	I915_WRITE(reg, val);