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Linus Torvalds
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May 1, 2013
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--- | ||
refs/heads/master: e2a8b0a779787314eca1061308a8182e6c5bfabd | ||
refs/heads/master: 5f56886521d6ddd3648777fae44d82382dd8c87f |
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What: /sys/devices/.../lpss_ltr/ | ||
Date: March 2013 | ||
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com> | ||
Description: | ||
The /sys/devices/.../lpss_ltr/ directory is only present for | ||
devices included into the Intel Lynxpoint Low Power Subsystem | ||
(LPSS). If present, it contains attributes containing the LTR | ||
mode and the values of LTR registers of the device. | ||
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What: /sys/devices/.../lpss_ltr/ltr_mode | ||
Date: March 2013 | ||
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com> | ||
Description: | ||
The /sys/devices/.../lpss_ltr/ltr_mode attribute contains an | ||
integer number (0 or 1) indicating whether or not the devices' | ||
LTR functionality is working in the software mode (1). | ||
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This attribute is read-only. If the device's runtime PM status | ||
is not "active", attempts to read from this attribute cause | ||
-EAGAIN to be returned. | ||
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What: /sys/devices/.../lpss_ltr/auto_ltr | ||
Date: March 2013 | ||
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com> | ||
Description: | ||
The /sys/devices/.../lpss_ltr/auto_ltr attribute contains the | ||
current value of the device's AUTO_LTR register (raw) | ||
represented as an 8-digit hexadecimal number. | ||
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This attribute is read-only. If the device's runtime PM status | ||
is not "active", attempts to read from this attribute cause | ||
-EAGAIN to be returned. | ||
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What: /sys/devices/.../lpss_ltr/sw_ltr | ||
Date: March 2013 | ||
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com> | ||
Description: | ||
The /sys/devices/.../lpss_ltr/auto_ltr attribute contains the | ||
current value of the device's SW_LTR register (raw) represented | ||
as an 8-digit hexadecimal number. | ||
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This attribute is read-only. If the device's runtime PM status | ||
is not "active", attempts to read from this attribute cause | ||
-EAGAIN to be returned. |
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13
trunk/Documentation/ABI/testing/sysfs-devices-power_resources_wakeup
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What: /sys/devices/.../power_resources_wakeup/ | ||
Date: April 2013 | ||
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com> | ||
Description: | ||
The /sys/devices/.../power_resources_wakeup/ directory is only | ||
present for device objects representing ACPI device nodes that | ||
require ACPI power resources for wakeup signaling. | ||
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If present, it contains symbolic links to device directories | ||
representing ACPI power resources that need to be turned on for | ||
the given device node to be able to signal wakeup. The names of | ||
the links are the same as the names of the directories they | ||
point to. |
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* Freescale i.MX PATA Controller | ||
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Required properties: | ||
- compatible: "fsl,imx27-pata" | ||
- reg: Address range of the PATA Controller | ||
- interrupts: The interrupt of the PATA Controller | ||
- clocks: the clocks for the PATA Controller | ||
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Example: | ||
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pata: pata@83fe0000 { | ||
compatible = "fsl,imx51-pata", "fsl,imx27-pata"; | ||
reg = <0x83fe0000 0x4000>; | ||
interrupts = <70>; | ||
clocks = <&clks 161>; | ||
status = "disabled"; | ||
}; |
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65
trunk/Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
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Generic ARM big LITTLE cpufreq driver's DT glue | ||
----------------------------------------------- | ||
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This is DT specific glue layer for generic cpufreq driver for big LITTLE | ||
systems. | ||
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Both required and optional properties listed below must be defined | ||
under node /cpus/cpu@x. Where x is the first cpu inside a cluster. | ||
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FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster | ||
must be present contiguously. Generic DT driver will check only node 'x' for | ||
cpu:x. | ||
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Required properties: | ||
- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt | ||
for details | ||
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Optional properties: | ||
- clock-latency: Specify the possible maximum transition latency for clock, | ||
in unit of nanoseconds. | ||
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Examples: | ||
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cpus { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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cpu@0 { | ||
compatible = "arm,cortex-a15"; | ||
reg = <0>; | ||
next-level-cache = <&L2>; | ||
operating-points = < | ||
/* kHz uV */ | ||
792000 1100000 | ||
396000 950000 | ||
198000 850000 | ||
>; | ||
clock-latency = <61036>; /* two CLK32 periods */ | ||
}; | ||
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cpu@1 { | ||
compatible = "arm,cortex-a15"; | ||
reg = <1>; | ||
next-level-cache = <&L2>; | ||
}; | ||
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cpu@100 { | ||
compatible = "arm,cortex-a7"; | ||
reg = <100>; | ||
next-level-cache = <&L2>; | ||
operating-points = < | ||
/* kHz uV */ | ||
792000 950000 | ||
396000 750000 | ||
198000 450000 | ||
>; | ||
clock-latency = <61036>; /* two CLK32 periods */ | ||
}; | ||
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cpu@101 { | ||
compatible = "arm,cortex-a7"; | ||
reg = <101>; | ||
next-level-cache = <&L2>; | ||
}; | ||
}; |
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