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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/…
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…arm-soc

Pull arm soc-specific updates from Arnd Bergmann:
 "This is stuff that does not fit well into another category and in
  particular is not related to a particular board.  The largest part in
  here is extending the am33xx support in the omap platform."

Fix up trivial conflicts in arch/arm/mach-{imx/mach-mx35_3ds.c, tegra/Makefile}

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (74 commits)
  ARM: LPC32xx: Add PWM support
  ARM: LPC32xx: Add PWM clock
  ARM: LPC32xx: Set system serial based on cpu unique id
  ARM: vexpress: Config option for early printk console
  ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile
  ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses
  ARM: vexpress: Add fixed regulator for SMSC
  ARM: vexpress: Add missing SP804 interrupt in motherboard's DTS files
  ARM: vexpress: Initial common clock support
  ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API
  ARM: EXYNOS: Add missing static storage class specifier in pmu.c file
  ARM: EXYNOS: Make combiner_init function static
  ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12
  ARM: versatile: Make plat-versatile clock optional
  ARM: vexpress: Check master site in daughterboard's sysctl operations
  ARM: vexpress: remove automatic errata workaround selection
  ARM: LPC32xx: Adjust to pl08x DMA interface changes
  ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset
  ARM: imx: fix mx51 ehci setup errors
  ARM: imx: make ehci power/oc polarities configurable
  ...
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Linus Torvalds committed Jul 23, 2012
2 parents 451ce7f + 233de29 commit 5e512d0
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Showing 91 changed files with 4,730 additions and 852 deletions.
11 changes: 7 additions & 4 deletions arch/arm/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -260,6 +260,7 @@ config ARCH_INTEGRATOR
select ICST
select GENERIC_CLOCKEVENTS
select PLAT_VERSATILE
select PLAT_VERSATILE_CLOCK
select PLAT_VERSATILE_FPGA_IRQ
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
Expand All @@ -277,6 +278,7 @@ config ARCH_REALVIEW
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
select PLAT_VERSATILE
select PLAT_VERSATILE_CLOCK
select PLAT_VERSATILE_CLCD
select ARM_TIMER_SP804
select GPIO_PL061 if GPIOLIB
Expand All @@ -295,6 +297,7 @@ config ARCH_VERSATILE
select ARCH_WANT_OPTIONAL_GPIOLIB
select NEED_MACH_IO_H if PCI
select PLAT_VERSATILE
select PLAT_VERSATILE_CLOCK
select PLAT_VERSATILE_CLCD
select PLAT_VERSATILE_FPGA_IRQ
select ARM_TIMER_SP804
Expand All @@ -307,14 +310,15 @@ config ARCH_VEXPRESS
select ARM_AMBA
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select HAVE_MACH_CLKDEV
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_PATA_PLATFORM
select ICST
select NO_IOPORT
select PLAT_VERSATILE
select PLAT_VERSATILE_CLCD
select REGULATOR_FIXED_VOLTAGE if REGULATOR
help
This enables support for the ARM Ltd Versatile Express boards.

Expand Down Expand Up @@ -567,6 +571,7 @@ config ARCH_LPC32XX
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select USE_OF
select HAVE_PWM
help
Support for the NXP LPC32XX family of processors

Expand Down Expand Up @@ -913,7 +918,7 @@ config ARCH_NOMADIK
select ARM_AMBA
select ARM_VIC
select CPU_ARM926T
select CLKDEV_LOOKUP
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select PINCTRL
select MIGHT_HAVE_CACHE_L2X0
Expand Down Expand Up @@ -1022,8 +1027,6 @@ source "arch/arm/mach-kirkwood/Kconfig"

source "arch/arm/mach-ks8695/Kconfig"

source "arch/arm/mach-lpc32xx/Kconfig"

source "arch/arm/mach-msm/Kconfig"

source "arch/arm/mach-mv78xx0/Kconfig"
Expand Down
26 changes: 26 additions & 0 deletions arch/arm/Kconfig.debug
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Expand Up @@ -310,6 +310,32 @@ choice
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.

config DEBUG_VEXPRESS_UART0_DETECT
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
depends on ARCH_VEXPRESS && CPU_CP15_MMU
help
This option enables a simple heuristic which tries to determine
the motherboard's memory map variant (original or RS1) and then
choose the relevant UART0 base address.

Note that this will only work with standard A-class core tiles,
and may fail with non-standard SMM or custom software models.

config DEBUG_VEXPRESS_UART0_CA9
bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
depends on ARCH_VEXPRESS
help
This option selects UART0 at 0x10009000. Except for custom models,
this applies only to the V2P-CA9 tile.

config DEBUG_VEXPRESS_UART0_RS1
bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
depends on ARCH_VEXPRESS
help
This option selects UART0 at 0x1c090000. This applies to most
of the tiles using the RS1 memory map, including all new A-class
core tiles, FPGA-based SMMs and software models.

config DEBUG_LL_UART_NONE
bool "No low-level debugging UART"
help
Expand Down
157 changes: 157 additions & 0 deletions arch/arm/boot/dts/ea3250.dts
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Original file line number Diff line number Diff line change
@@ -0,0 +1,157 @@
/*
* Embedded Artists LPC3250 board
*
* Copyright 2012 Roland Stigge <stigge@antcom.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/

/dts-v1/;
/include/ "lpc32xx.dtsi"

/ {
model = "Embedded Artists LPC3250 board based on NXP LPC3250";
compatible = "ea,ea3250", "nxp,lpc3250";
#address-cells = <1>;
#size-cells = <1>;

memory {
device_type = "memory";
reg = <0 0x4000000>;
};

ahb {
mac: ethernet@31060000 {
phy-mode = "rmii";
use-iram;
};

/* Here, choose exactly one from: ohci, usbd */
ohci@31020000 {
transceiver = <&isp1301>;
status = "okay";
};

/*
usbd@31020000 {
transceiver = <&isp1301>;
status = "okay";
};
*/

/* 128MB Flash via SLC NAND controller */
slc: flash@20020000 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;

nxp,wdr-clks = <14>;
nxp,wwidth = <260000000>;
nxp,whold = <104000000>;
nxp,wsetup = <200000000>;
nxp,rdr-clks = <14>;
nxp,rwidth = <34666666>;
nxp,rhold = <104000000>;
nxp,rsetup = <200000000>;
nand-on-flash-bbt;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */

mtd0@00000000 {
label = "ea3250-boot";
reg = <0x00000000 0x00080000>;
read-only;
};

mtd1@00080000 {
label = "ea3250-uboot";
reg = <0x00080000 0x000c0000>;
read-only;
};

mtd2@00140000 {
label = "ea3250-kernel";
reg = <0x00140000 0x00400000>;
};

mtd3@00540000 {
label = "ea3250-rootfs";
reg = <0x00540000 0x07ac0000>;
};
};

apb {
uart5: serial@40090000 {
status = "okay";
};

uart3: serial@40080000 {
status = "okay";
};

uart6: serial@40098000 {
status = "okay";
};

i2c1: i2c@400A0000 {
clock-frequency = <100000>;

eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};

eeprom@57 {
compatible = "at,24c64";
reg = <0x57>;
};

uda1380: uda1380@18 {
compatible = "nxp,uda1380";
reg = <0x18>;
power-gpio = <&gpio 0x59 0>;
reset-gpio = <&gpio 0x51 0>;
dac-clk = "wspll";
};

pca9532: pca9532@60 {
compatible = "nxp,pca9532";
gpio-controller;
#gpio-cells = <2>;
reg = <0x60>;
};
};

i2c2: i2c@400A8000 {
clock-frequency = <100000>;
};

i2cusb: i2c@31020300 {
clock-frequency = <100000>;

isp1301: usb-transceiver@2d {
compatible = "nxp,isp1301";
reg = <0x2d>;
};
};

sd@20098000 {
wp-gpios = <&pca9532 5 0>;
cd-gpios = <&pca9532 4 0>;
cd-inverted;
bus-width = <4>;
status = "okay";
};
};

fab {
uart1: serial@40014000 {
status = "okay";
};
};
};
};
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