---

yaml
---
r: 344343
b: refs/heads/master
c: af170c5
h: refs/heads/master
i:
  344341: 2efd8e3
  344339: c4475e4
  344335: 147f5c8
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 4939e27d46fee2609f2112f85f7f7cbd952075dc
+refs/heads/master: af170c5061dd78512c469e6e2d211980cdb2c193

trunk/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt

@@ -6,15 +6,9 @@ Required properties:
 - interrupt-controller: Identifies the node as an interrupt controller.
 - #interrupt-cells: The number of cells to define the interrupts. Should be 1.
   The cell is the IRQ number
-
 - reg: Should contain PMIC registers location and length. First pair
   for the main interrupt registers, second pair for the per-CPU
-  interrupt registers. For this last pair, to be compliant with SMP
-  support, the "virtual" must be use (For the record, these registers
-  automatically map to the interrupt controller registers of the
-  current CPU)
-
-
+  interrupt registers
 
 Example:
 
@@ -24,6 +18,6 @@ Example:
               #address-cells = <1>;
               #size-cells = <1>;
               interrupt-controller;
-              reg = <0xd0020a00 0x1d0>,
-                    <0xd0021070 0x58>;
+              reg = <0xd0020000 0x1000>,
+                    <0xd0021000 0x1000>;
         };

trunk/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt

@@ -5,7 +5,6 @@ Required properties:
 - compatible: Should be "marvell,armada-370-xp-timer"
 - interrupts: Should contain the list of Global Timer interrupts
 - reg: Should contain the base address of the Global Timer registers
-- clocks: clock driving the timer hardware
 
 Optional properties:
 - marvell,timer-25Mhz: Tells whether the Global timer supports the 25

trunk/Documentation/devicetree/bindings/arm/l2cc.txt

@@ -10,12 +10,6 @@ Required properties:
 	"arm,pl310-cache"
 	"arm,l220-cache"
 	"arm,l210-cache"
-	"marvell,aurora-system-cache": Marvell Controller designed to be
-     compatible with the ARM one, with system cache mode (meaning
-     maintenance operations on L1 are broadcasted to the L2 and L2
-     performs the same operation).
-	"marvell,"aurora-outer-cache: Marvell Controller designed to be
-	 compatible with the ARM one with outer cache mode.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
@@ -35,9 +29,6 @@ Optional properties:
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
 - interrupts : 1 combined interrupt.
-- cache-id-part: cache id part number to be used if it is not present
-  on hardware
-- wt-override: If present then L2 is forced to Write through mode
 
 Example: