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yaml
---
r: 155590
b: refs/heads/master
c: 5bc6e3c
h: refs/heads/master
v: v3
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Graf Yang authored and Mike Frysinger committed Jul 16, 2009
1 parent ececb08 commit 5fb72a7
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Showing 2 changed files with 18 additions and 7 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: f574a76a3b19848ac61814756716e26f85f2c3f7
refs/heads/master: 5bc6e3cfe6db5f33c60f042a9ba203431f334756
23 changes: 17 additions & 6 deletions trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c
Original file line number Diff line number Diff line change
Expand Up @@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
}

/* Cover L1 memory. One 4M area for code and data each is enough. */
if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
d_tbl[i_d].addr = L1_DATA_A_START;
d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
if (cpu == 0) {
if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
d_tbl[i_d].addr = L1_DATA_A_START;
d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
}
i_tbl[i_i].addr = L1_CODE_START;
i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
}
i_tbl[i_i].addr = L1_CODE_START;
i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;

#ifdef CONFIG_SMP
else {
if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
d_tbl[i_d].addr = COREB_L1_DATA_A_START;
d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
}
i_tbl[i_i].addr = COREB_L1_CODE_START;
i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
}
#endif
first_switched_dcplb = i_d;
first_switched_icplb = i_i;

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