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…erex/alsa * 'linus' of master.kernel.org:/pub/scm/linux/kernel/git/perex/alsa: (212 commits) [PATCH] Fix breakage with CONFIG_SYSFS_DEPRECATED [ALSA] version 1.0.14rc2 [ALSA] ASoC documentation updates [ALSA] ca0106 - Add missing sysfs device assignment [ALSA] aoa i2sbus: Stop Apple i2s DMA gracefully [ALSA] hda-codec - Add support for Fujitsu PI1556 Realtek ALC880 [ALSA] aoa: remove suspend/resume printks [ALSA] Fix possible deadlocks in sequencer at removal of ports [ALSA] emu10k1 - Fix STAC9758 front channel [ALSA] soc - Clean up with kmemdup() [ALSA] snd-ak4114: Fix two array overflows [ALSA] ac97_bus power management [ALSA] usbaudio - Add support for Edirol UA-101 [ALSA] hda-codec - Add ALC861VD/ALC660VD support [ALSA] soc - ASoC 0.13 Sharp poodle machine [ALSA] soc - ASoC 0.13 Sharp tosa machine [ALSA] soc - ASoC 0.13 spitz machine [ALSA] soc - ASoC Sharp corgi machine [ALSA] soc - ASoC 0.13 pxa2xx DMA [ALSA] soc - ASoC 0.13 pxa2xx AC97 driver ...
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ASoC currently supports the three main Digital Audio Interfaces (DAI) found on | ||
SoC controllers and portable audio CODECS today, namely AC97, I2S and PCM. | ||
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AC97 | ||
==== | ||
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AC97 is a five wire interface commonly found on many PC sound cards. It is | ||
now also popular in many portable devices. This DAI has a reset line and time | ||
multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines. | ||
The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the | ||
frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97 | ||
frame is 21uS long and is divided into 13 time slots. | ||
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The AC97 specification can be found at :- | ||
http://www.intel.com/design/chipsets/audio/ac97_r23.pdf | ||
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I2S | ||
=== | ||
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I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and | ||
Rx lines are used for audio transmision, whilst the bit clock (BCLK) and | ||
left/right clock (LRC) synchronise the link. I2S is flexible in that either the | ||
controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock | ||
usually varies depending on the sample rate and the master system clock | ||
(SYSCLK). LRCLK is the same as the sample rate. A few devices support separate | ||
ADC and DAC LRCLK's, this allows for similtanious capture and playback at | ||
different sample rates. | ||
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I2S has several different operating modes:- | ||
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o I2S - MSB is transmitted on the falling edge of the first BCLK after LRC | ||
transition. | ||
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o Left Justified - MSB is transmitted on transition of LRC. | ||
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o Right Justified - MSB is transmitted sample size BCLK's before LRC | ||
transition. | ||
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PCM | ||
=== | ||
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PCM is another 4 wire interface, very similar to I2S, that can support a more | ||
flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used | ||
to synchronise the link whilst the Tx and Rx lines are used to transmit and | ||
receive the audio data. Bit clock usually varies depending on sample rate | ||
whilst sync runs at the sample rate. PCM also supports Time Division | ||
Multiplexing (TDM) in that several devices can use the bus similtaniuosly (This | ||
is sometimes referred to as network mode). | ||
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Common PCM operating modes:- | ||
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o Mode A - MSB is transmitted on falling edge of first BCLK after FRAME/SYNC. | ||
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o Mode B - MSB is transmitted on rising edge of FRAME/SYNC. |
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