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yaml --- r: 331429 b: refs/heads/master c: f821e34 h: refs/heads/master i: 331427: 9db86e2 v: v3
git-mirror · Sep 27, 2012 · 602688b · 602688b
1 parent d6524ce
commit 602688b
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Showing 3 changed files with 47 additions and 31 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 8a415c4be5401f94d7be075682b8c0f43440329a
+refs/heads/master: f821e349cf2539bc7752652ef7b60030c1fc49fb
diff --git a/trunk/arch/m68k/include/asm/m527xsim.h b/trunk/arch/m68k/include/asm/m527xsim.h
@@ -194,9 +194,23 @@
 #define MCFGPIO_IRQ_MAX			8
 #define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD		(MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL	(MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS		(MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS		(MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM	(MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C	(MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART	(MCF_IPSBAR + 0x100048)
 #define MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10004A)
 #define MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10004C)
-#endif
+
+#define UART0_ENABLE_MASK	0x000f
+#define UART1_ENABLE_MASK	0x0ff0
+#define UART2_ENABLE_MASK	0x3000
+#endif /* CONFIG_M5271 */
 
 #ifdef CONFIG_M5275
 #define MCFGPIO_PODR_BUSCTL	(MCF_IPSBAR + 0x100004)
@@ -289,8 +303,26 @@
 #define MCFGPIO_IRQ_MAX			8
 #define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE
 
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD		(MCF_IPSBAR + 0x100070)
+#define MCFGPIO_PAR_CS		(MCF_IPSBAR + 0x100071)
+#define MCFGPIO_PAR_BUSCTL	(MCF_IPSBAR + 0x100072)
+#define MCFGPIO_PAR_USB		(MCF_IPSBAR + 0x100076)
+#define MCFGPIO_PAR_FEC0HL	(MCF_IPSBAR + 0x100078)
+#define MCFGPIO_PAR_FEC1HL	(MCF_IPSBAR + 0x100079)
+#define MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10007A)
+#define MCFGPIO_PAR_UART	(MCF_IPSBAR + 0x10007C)
 #define MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10007E)
-#endif
+#define MCFGPIO_PAR_SDRAM	(MCF_IPSBAR + 0x100080)
+#define MCFGPIO_PAR_FECI2C	(MCF_IPSBAR + 0x100082)
+#define MCFGPIO_PAR_BS		(MCF_IPSBAR + 0x100084)
+
+#define UART0_ENABLE_MASK	0x000f
+#define UART1_ENABLE_MASK	0x00f0
+#define UART2_ENABLE_MASK	0x3f00
+#endif /* CONFIG_M5275 */
 
 /*
  * PIT timer base addresses.
@@ -310,22 +342,6 @@
 #define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x130005)
 #define MCFEPORT_EPFR		(MCF_IPSBAR + 0x130006)
 
-/*
- *	GPIO pins setups to enable the UARTs.
- */
-#ifdef CONFIG_M5271
-#define MCF_GPIO_PAR_UART	0x100048	/* PAR UART address */
-#define UART0_ENABLE_MASK	0x000f
-#define UART1_ENABLE_MASK	0x0ff0
-#define UART2_ENABLE_MASK	0x3000
-#endif
-#ifdef CONFIG_M5275
-#define MCF_GPIO_PAR_UART	0x10007c	/* PAR UART address */
-#define UART0_ENABLE_MASK	0x000f
-#define UART1_ENABLE_MASK	0x00f0
-#define UART2_ENABLE_MASK	0x3f00 
-#endif
-
 /*
  *  Reset Control Unit (relative to IPSBAR).
  */

diff --git a/trunk/arch/m68k/platform/coldfire/m527x.c b/trunk/arch/m68k/platform/coldfire/m527x.c
@@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void)
 	/*
 	 * External Pin Mask Setting & Enable External Pin for Interface
 	 */
-	sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+	sepmask = readw(MCFGPIO_PAR_UART);
 	sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
-	writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+	writew(sepmask, MCFGPIO_PAR_UART);
 }
 
 /***************************************************************************/
@@ -67,19 +67,19 @@ static void __init m527x_fec_init(void)
 
 	/* Set multi-function pins to ethernet mode for fec0 */
 #if defined(CONFIG_M5271)
-	v = readb(MCF_IPSBAR + 0x100047);
-	writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
+	v = readb(MCFGPIO_PAR_FECI2C);
+	writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
 #else
-	par = readw(MCF_IPSBAR + 0x100082);
-	writew(par | 0xf00, MCF_IPSBAR + 0x100082);
-	v = readb(MCF_IPSBAR + 0x100078);
-	writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
+	par = readw(MCFGPIO_PAR_FECI2C);
+	writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
+	v = readb(MCFGPIO_PAR_FEC0HL);
+	writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
 
 	/* Set multi-function pins to ethernet mode for fec1 */
-	par = readw(MCF_IPSBAR + 0x100082);
-	writew(par | 0xa0, MCF_IPSBAR + 0x100082);
-	v = readb(MCF_IPSBAR + 0x100079);
-	writeb(v | 0xc0, MCF_IPSBAR + 0x100079);
+	par = readw(MCFGPIO_PAR_FECI2C);
+	writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
+	v = readb(MCFGPIO_PAR_FEC1HL);
+	writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
 #endif
 }