drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc

@@ -149,13 +149,9 @@ watchdog_clear:
 //
 wait_donez:
 	trace_set(T_WAIT);
-	mov $r8 0x818
-	shl b32 $r8 6
-	iowr I[$r8 + 0x000] $r10
+	nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
 	wait_donez_ne:
-		mov $r8 0x400
-		shl b32 $r8 6
-		iord $r8 I[$r8 + 0x000]
+		nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
 		xbit $r8 $r8 $r10
 		bra ne #wait_donez_ne
 	trace_clr(T_WAIT)

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc

@@ -141,9 +141,7 @@ init:
 #endif
 
 	// initialise context base, and size tracking
-	mov $r2 0x800
-	shl b32 $r2 6
-	iord $r2 I[$r2 + 0x100]	// CC_SCRATCH[1], initial base
+	nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
 	clear b32 $r3		// track GPC context size here
 
 	// set mmctx base addresses now so we don't have to do it later,
@@ -198,13 +196,10 @@ init:
 	add b32 $r3 $r15
 
 	// save context size, and tell HUB we're done
-	mov $r1 0x800
-	shl b32 $r1 6
-	iowr I[$r1 + 0x100] $r3		// CC_SCRATCH[1]  = context size
-	add b32 $r1 0x800
+	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
 	clear b32 $r2
 	bset $r2 31
-	iowr I[$r1 + 0x000] $r2		// CC_SCRATCH[0] |= 0x80000000
+	nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)
 
 // Main program loop, very simple, sleeps until woken up by the interrupt
 // handler, pulls a command from the queue and executes its handler
@@ -249,6 +244,7 @@ ih:
 	push $r13
 	push $r14
 	push $r15
+	clear b32 $r0
 
 	// incoming fifo command?
 	iord $r10 I[$r0 + 0x200]	// INTR