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Linus Torvalds
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Feb 19, 2007
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S3C2410 DMA | ||
=========== | ||
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Introduction | ||
------------ | ||
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The kernel provides an interface to manage DMA transfers | ||
using the DMA channels in the cpu, so that the central | ||
duty of managing channel mappings, and programming the | ||
channel generators is in one place. | ||
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DMA Channel Ordering | ||
-------------------- | ||
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Many of the range do not have connections for the DMA | ||
channels to all sources, which means that some devices | ||
have a restricted number of channels that can be used. | ||
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To allow flexibilty for each cpu type and board, the | ||
dma code can be given an dma ordering structure which | ||
allows the order of channel search to be specified, as | ||
well as allowing the prohibition of certain claims. | ||
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struct s3c24xx_dma_order has a list of channels, and | ||
each channel within has a slot for a list of dma | ||
channel numbers. The slots are searched in order, for | ||
the presence of a dma channel number with DMA_CH_VALID | ||
orred in. | ||
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If the order has the flag DMA_CH_NEVER set, then after | ||
checking the channel list, the system will return no | ||
found channel, thus denying the request. | ||
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A board support file can call s3c24xx_dma_order_set() | ||
to register an complete ordering set. The routine will | ||
copy the data, so the original can be discared with | ||
__initdata. | ||
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Authour | ||
------- | ||
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Ben Dooks, | ||
Copyright (c) 2007 Ben Dooks, Simtec Electronics | ||
Licensed under the GPL v2 |
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