Skip to content

Commit

Permalink
x86, intr-remap: Remove IRTE setup duplicate code
Browse files Browse the repository at this point in the history
Remove IRTE setup duplicate code with prepare_irte().

Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
LKML-Reference: <20100827181049.095067319@sbsiddha-MOBL3.sc.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
  • Loading branch information
Suresh Siddha authored and H. Peter Anvin committed Sep 16, 2010
1 parent 75e3cfb commit 62a92f4
Show file tree
Hide file tree
Showing 2 changed files with 29 additions and 25 deletions.
27 changes: 27 additions & 0 deletions arch/x86/include/asm/irq_remapping.h
Original file line number Diff line number Diff line change
Expand Up @@ -3,4 +3,31 @@

#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)

#ifdef CONFIG_INTR_REMAP
static inline void prepare_irte(struct irte *irte, int vector,
unsigned int dest)
{
memset(irte, 0, sizeof(*irte));

irte->present = 1;
irte->dst_mode = apic->irq_dest_mode;
/*
* Trigger mode in the IRTE will always be edge, and for IO-APIC, the
* actual level or edge trigger will be setup in the IO-APIC
* RTE. This will help simplify level triggered irq migration.
* For more details, see the comments (in io_apic.c) explainig IO-APIC
* irq migration in the presence of interrupt-remapping.
*/
irte->trigger_mode = 0;
irte->dlvry_mode = apic->irq_delivery_mode;
irte->vector = vector;
irte->dest_id = IRTE_DEST(dest);
irte->redir_hint = 1;
}
#else
static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
{
}
#endif

#endif /* _ASM_X86_IRQ_REMAPPING_H */
27 changes: 2 additions & 25 deletions arch/x86/kernel/apic/io_apic.c
Original file line number Diff line number Diff line change
Expand Up @@ -1377,22 +1377,7 @@ int setup_ioapic_entry(int apic_id, int irq,
if (index < 0)
panic("Failed to allocate IRTE for ioapic %d\n", apic_id);

memset(&irte, 0, sizeof(irte));

irte.present = 1;
irte.dst_mode = apic->irq_dest_mode;
/*
* Trigger mode in the IRTE will always be edge, and the
* actual level or edge trigger will be setup in the IO-APIC
* RTE. This will help simplify level triggered irq migration.
* For more details, see the comments above explainig IO-APIC
* irq migration in the presence of interrupt-remapping.
*/
irte.trigger_mode = 0;
irte.dlvry_mode = apic->irq_delivery_mode;
irte.vector = vector;
irte.dest_id = IRTE_DEST(destination);
irte.redir_hint = 1;
prepare_irte(&irte, vector, destination);

/* Set source-id of interrupt request */
set_ioapic_sid(&irte, apic_id);
Expand Down Expand Up @@ -3336,15 +3321,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
ir_index = map_irq_to_irte_handle(irq, &sub_handle);
BUG_ON(ir_index == -1);

memset (&irte, 0, sizeof(irte));

irte.present = 1;
irte.dst_mode = apic->irq_dest_mode;
irte.trigger_mode = 0; /* edge */
irte.dlvry_mode = apic->irq_delivery_mode;
irte.vector = cfg->vector;
irte.dest_id = IRTE_DEST(dest);
irte.redir_hint = 1;
prepare_irte(&irte, cfg->vector, dest);

/* Set source-id of interrupt request */
if (pdev)
Expand Down

0 comments on commit 62a92f4

Please sign in to comment.