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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/…
…git/arm/arm-soc Pull ARM 64-bit DT updates from Olof Johansson: "This is the first release where we split up the 64-bit contributions a bit more, and in particular we are having a separate DT branch for them. Contents: - New devices added to Broadcom NorthStar2 - Misc fixes for Exynos7 boards - QCOM updates for MSM8916 - Rockchip tweaks for rk3368 SoC and eval board - A series of fixes for APM X-Gene v1 and v2 - Renesas R8A7795 CPU/PSCI additions - Marvell Berlin4CT PSCI, cpuidle, watchdog portions - Freescale LS1043a SoC and dev board support + some treewide or other misc changes" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits) dts/ls2080a: Update DTSI to add support of SP805 WDT Documentation: DT: Add entry for ARM SP805-WDT arm64: dts: X-Gene v2: I2C1 clock is always on arm64: dts: X-Gene v1: I2C0 clock is always on arm64: dts: Fix to use standard DT node names for X-Gene 1 and X-Gene 2 platforms arm64: dts: hikey: add label properties to UARTs arm64: dts: apq8016-sbc: add label properties for UART, I2C, and SPI arm64: dts: apq8016-sbc: enable UART0 on LS connector arm64: dts: juno: Add idle-states to device tree arm64: dts: Added syscon-reboot node for FSL's LS2080A SoC arm64: dts: add LS1043a-RDB board support arm64: dts: add Freescale LS1043a SoC support Documentation: DT: Add entry for Freescale LS1043a-RDB board arm64: dts: uniphier: add PH1-LD10 SoC/board support arm64: renesas: r8a7795: fix SATA clock assignment arm64: dts: salvator-x: Enable SATA controller arm64: dts: r8a7795: Add SATA controller node arm64: renesas: r8a7795: add internal delay for i2c IPs arm64: renesas: salvator-x: Add board part number to DT bindings arm64: dts: r8a7795: Add pmu device nodes ...
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* ARM SP805 Watchdog Timer (WDT) Controller | ||
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SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that | ||
can be used to identify the peripheral type, vendor, and revision. | ||
This value can be used for driver matching. | ||
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As SP805 WDT is a primecell IP, it follows the base bindings specified in | ||
'arm/primecell.txt' | ||
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Required properties: | ||
- compatible : Should be "arm,sp805-wdt", "arm,primecell" | ||
- reg : Base address and size of the watchdog timer registers. | ||
- clocks : From common clock binding. | ||
First clock is PCLK and the second is WDOGCLK. | ||
WDOGCLK can be equal to or be a sub-multiple of the PCLK frequency. | ||
- clock-names : From common clock binding. | ||
Shall be "apb_pclk" for first clock and "wdog_clk" for the | ||
second one. | ||
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Optional properties: | ||
- interrupts : Should specify WDT interrupt number. | ||
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Examples: | ||
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cluster1_core0_watchdog: wdt@c000000 { | ||
compatible = "arm,sp805-wdt", "arm,primecell"; | ||
reg = <0x0 0xc000000 0x0 0x1000>; | ||
clocks = <&clockgen 4 3>, <&clockgen 4 3>; | ||
clock-names = "apb_pclk", "wdog_clk"; | ||
}; | ||
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&xgenet { | ||
status = "ok"; | ||
}; | ||
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&mmc0 { | ||
status = "ok"; | ||
}; |
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