---

yaml
---
r: 249306
b: refs/heads/master
c: 5672cfa
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 909f43a0c6340284503d20650ea9bb74efa10c39
+refs/heads/master: 5672cfa335d2518f3168ff1ad654d8e392181f51

trunk/drivers/staging/brcm80211/util/aiutils.c

@@ -138,7 +138,6 @@ void ai_scan(si_t *sih, void *regs, uint devid)
 	default:
 		SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
 			  sih->bustype));
-		ASSERT(0);
 		return;
 	}
 	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
@@ -322,24 +321,15 @@ void *ai_setcoreidx(si_t *sih, uint coreidx)
 	if (coreidx >= sii->numcores)
 		return NULL;
 
-	/*
-	 * If the user has provided an interrupt mask enabled function,
-	 * then assert interrupts are disabled before switching the core.
-	 */
-	ASSERT((sii->intrsenabled_fn == NULL)
-	       || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));
-
 	switch (sih->bustype) {
 	case SI_BUS:
 		/* map new one */
 		if (!sii->regs[coreidx]) {
 			sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
-			ASSERT(GOODREGS(sii->regs[coreidx]));
 		}
 		sii->curmap = regs = sii->regs[coreidx];
 		if (!sii->wrappers[coreidx]) {
 			sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
-			ASSERT(GOODREGS(sii->wrappers[coreidx]));
 		}
 		sii->curwrap = sii->wrappers[coreidx];
 		break;
@@ -359,7 +349,6 @@ void *ai_setcoreidx(si_t *sih, uint coreidx)
 		break;
 
 	default:
-		ASSERT(0);
 		regs = NULL;
 		break;
 	}
@@ -494,10 +483,6 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
 
 	sii = SI_INFO(sih);
 
-	ASSERT(GOODIDX(coreidx));
-	ASSERT(regoff < SI_CORE_SIZE);
-	ASSERT((val & ~mask) == 0);
-
 	if (coreidx >= SI_MAXCORES)
 		return 0;
 
@@ -508,7 +493,6 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
 		if (!sii->regs[coreidx]) {
 			sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
 						     SI_CORE_SIZE);
-			ASSERT(GOODREGS(sii->regs[coreidx]));
 		}
 		r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
 	} else if (sih->bustype == PCI_BUS) {
@@ -548,7 +532,6 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
 		r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
 				regoff);
 	}
-	ASSERT(r != NULL);
 
 	/* mask and set */
 	if (mask || val) {
@@ -578,7 +561,6 @@ void ai_core_disable(si_t *sih, u32 bits)
 
 	sii = SI_INFO(sih);
 
-	ASSERT(GOODREGS(sii->curwrap));
 	ai = sii->curwrap;
 
 	/* if core is already in reset, just return */
@@ -605,7 +587,6 @@ void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
 	volatile u32 dummy;
 
 	sii = SI_INFO(sih);
-	ASSERT(GOODREGS(sii->curwrap));
 	ai = sii->curwrap;
 
 	/*
@@ -640,11 +621,8 @@ void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
 		return;
 	}
 
-	ASSERT(GOODREGS(sii->curwrap));
 	ai = sii->curwrap;
 
-	ASSERT((val & ~mask) == 0);
-
 	if (mask || val) {
 		w = ((R_REG(&ai->ioctrl) & ~mask) | val);
 		W_REG(&ai->ioctrl, w);
@@ -664,11 +642,8 @@ u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
 		return 0;
 	}
 
-	ASSERT(GOODREGS(sii->curwrap));
 	ai = sii->curwrap;
 
-	ASSERT((val & ~mask) == 0);
-
 	if (mask || val) {
 		w = ((R_REG(&ai->ioctrl) & ~mask) | val);
 		W_REG(&ai->ioctrl, w);
@@ -689,12 +664,8 @@ u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
 		return 0;
 	}
 
-	ASSERT(GOODREGS(sii->curwrap));
 	ai = sii->curwrap;
 
-	ASSERT((val & ~mask) == 0);
-	ASSERT((mask & ~SISF_CORE_BITS) == 0);
-
 	if (mask || val) {
 		w = ((R_REG(&ai->iostatus) & ~mask) | val);
 		W_REG(&ai->iostatus, w);

trunk/drivers/staging/brcm80211/util/bcmutils.c

@@ -280,17 +280,13 @@ void pktq_flush(struct pktq *pq, bool dir,
 	int prec;
 	for (prec = 0; prec < pq->num_prec; prec++)
 		pktq_pflush(pq, prec, dir, fn, arg);
-	if (fn == NULL)
-		ASSERT(pq->len == 0);
 }
 #endif /* BRCM_FULLMAC */
 
 void pktq_init(struct pktq *pq, int num_prec, int max_len)
 {
 	int prec;
 
-	ASSERT(num_prec > 0 && num_prec <= PKTQ_MAX_PREC);
-
 	/* pq is variable size; only zero out what's requested */
 	memset(pq, 0,
 	      offsetof(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec));

trunk/drivers/staging/brcm80211/util/bcmwifi.c

@@ -60,16 +60,13 @@ u8 wf_chspec_ctlchan(chanspec_t chspec)
 		return CHSPEC_CHANNEL(chspec);
 	} else {
 		/* we only support 40MHZ with sidebands */
-		ASSERT(CHSPEC_BW(chspec) == WL_CHANSPEC_BW_40);
 		/* chanspec channel holds the centre frequency, use that and the
 		 * side band information to reconstruct the control channel number
 		 */
 		if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_UPPER) {
 			/* control chan is the upper 20 MHZ SB of the 40MHZ channel */
 			ctl_chan = UPPER_20_SB(CHSPEC_CHANNEL(chspec));
 		} else {
-			ASSERT(CHSPEC_CTL_SB(chspec) ==
-			       WL_CHANSPEC_CTL_SB_LOWER);
 			/* control chan is the lower 20 MHZ SB of the 40MHZ channel */
 			ctl_chan = LOWER_20_SB(CHSPEC_CHANNEL(chspec));
 		}

trunk/drivers/staging/brcm80211/util/hnddma.c

@@ -293,23 +293,9 @@ struct hnddma_pub *dma_attach(char *name, si_t *sih,
 
 	di->msg_level = msg_level ? msg_level : &dma_msg_level;
 
-	/* old chips w/o sb is no longer supported */
-	ASSERT(sih != NULL);
-
 	di->dma64 = ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
 
-	/* check arguments */
-	ASSERT(ISPOWEROF2(ntxd));
-	ASSERT(ISPOWEROF2(nrxd));
-
-	if (nrxd == 0)
-		ASSERT(dmaregsrx == NULL);
-	if (ntxd == 0)
-		ASSERT(dmaregstx == NULL);
-
 	/* init dma reg pointer */
-	ASSERT(ntxd <= D64MAXDD);
-	ASSERT(nrxd <= D64MAXDD);
 	di->d64txregs = (dma64regs_t *) dmaregstx;
 	di->d64rxregs = (dma64regs_t *) dmaregsrx;
 	di->hnddma.di_fn = (const di_fcn_t *)&dma64proc;
@@ -488,7 +474,6 @@ dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
 #else
 	if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
 #endif				/* defined(__mips__) && defined(IL_BIGENDIAN) */
-		ASSERT((PHYSADDRHI(pa) & PCI64ADDR_HIGH) == 0);
 
 		W_SM(&ddring[outidx].addrlow,
 		     BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
@@ -499,11 +484,9 @@ dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
 	} else {
 		/* address extension for 32-bit PCI */
 		u32 ae;
-		ASSERT(di->addrext);
 
 		ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
 		PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
-		ASSERT(PHYSADDRHI(pa) == 0);
 
 		ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE;
 		W_SM(&ddring[outidx].addrlow,
@@ -544,10 +527,6 @@ static void _dma_detach(dma_info_t *di)
 
 	DMA_TRACE(("%s: dma_detach\n", di->name));
 
-	/* shouldn't be here if descriptors are unreclaimed */
-	ASSERT(di->txin == di->txout);
-	ASSERT(di->rxin == di->rxout);
-
 	/* free dma descriptor rings */
 	if (di->txd64)
 		pci_free_consistent(di->pbus, di->txdalloc,
@@ -602,14 +581,12 @@ static bool _dma_isaddrext(dma_info_t *di)
 		if (!_dma64_addrext(di->d64txregs)) {
 			DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
 				   "AE set\n", di->name));
-			ASSERT(0);
 		}
 		return true;
 	} else if (di->d64rxregs != NULL) {
 		if (!_dma64_addrext(di->d64rxregs)) {
 			DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
 				   "AE set\n", di->name));
-			ASSERT(0);
 		}
 		return true;
 	}
@@ -642,8 +619,6 @@ static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
 	} else {
 		/* DMA64 32bits address extension */
 		u32 ae;
-		ASSERT(di->addrext);
-		ASSERT(PHYSADDRHI(pa) == 0);
 
 		/* shift the high bit(s) from pa to ae */
 		ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >>
@@ -783,7 +758,6 @@ static void *BCMFASTPATH _dma_rx(dma_info_t *di)
 #ifdef BCMDBG
 		if (resid > 0) {
 			uint cur;
-			ASSERT(p == NULL);
 			cur =
 			    B2I(((R_REG(&di->d64rxregs->status0) &
 				  D64_RS0_CD_MASK) -
@@ -874,10 +848,7 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
 		pa = pci_map_single(di->pbus, p->data,
 			di->rxbufsize, PCI_DMA_FROMDEVICE);
 
-		ASSERT(IS_ALIGNED(PHYSADDRLO(pa), 4));
-
 		/* save the free packet pointer */
-		ASSERT(di->rxp[rxout] == NULL);
 		di->rxp[rxout] = p;
 
 		/* reset flags for each descriptor */
@@ -1019,8 +990,6 @@ static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
 		return 0;
 	}
 
-	ASSERT((flags & ~mask) == 0);
-
 	dmactrlflags &= ~mask;
 	dmactrlflags |= flags;
 
@@ -1053,18 +1022,13 @@ static unsigned long _dma_getvar(dma_info_t *di, const char *name)
 {
 	if (!strcmp(name, "&txavail"))
 		return (unsigned long)&(di->hnddma.txavail);
-	else {
-		ASSERT(0);
-	}
 	return 0;
 }
 
 static
 u8 dma_align_sizetobits(uint size)
 {
 	u8 bitpos = 0;
-	ASSERT(size);
-	ASSERT(!(size & (size - 1)));
 	while (size >>= 1) {
 		bitpos++;
 	}
@@ -1230,12 +1194,8 @@ static bool dma64_alloc(dma_info_t *di, uint direction)
 		di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
 		PHYSADDRLOSET(di->txdpa,
 			      PHYSADDRLO(di->txdpaorig) + di->txdalign);
-		/* Make sure that alignment didn't overflow */
-		ASSERT(PHYSADDRLO(di->txdpa) >= PHYSADDRLO(di->txdpaorig));
-
 		PHYSADDRHISET(di->txdpa, PHYSADDRHI(di->txdpaorig));
 		di->txdalloc = alloced;
-		ASSERT(IS_ALIGNED((unsigned long)di->txd64, align));
 	} else {
 		va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
 			&alloced, &di->rxdpaorig);
@@ -1248,12 +1208,8 @@ static bool dma64_alloc(dma_info_t *di, uint direction)
 		di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
 		PHYSADDRLOSET(di->rxdpa,
 			      PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
-		/* Make sure that alignment didn't overflow */
-		ASSERT(PHYSADDRLO(di->rxdpa) >= PHYSADDRLO(di->rxdpaorig));
-
 		PHYSADDRHISET(di->rxdpa, PHYSADDRHI(di->rxdpaorig));
 		di->rxdalloc = alloced;
-		ASSERT(IS_ALIGNED((unsigned long)di->rxd64, align));
 	}
 
 	return true;
@@ -1396,7 +1352,6 @@ static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit)
 		flags |= D64_CTRL1_EOT;
 
 	dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
-	ASSERT(di->txp[txout] == NULL);
 
 	/* save the buffer pointer - used by dma_getpos */
 	di->txp[txout] = buf;
@@ -1501,7 +1456,6 @@ static int BCMFASTPATH dma64_txfast(dma_info_t *di, struct sk_buff *p0,
 				pa = map->segs[j - 1].addr;
 			}
 			dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
-			ASSERT(di->txp[txout] == NULL);
 
 			txout = NEXTTXD(txout);
 		}
@@ -1648,9 +1602,6 @@ static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall)
 	void *rxp;
 	dmaaddr_t pa;
 
-	/* if forcing, dma engine must be disabled */
-	ASSERT(!forceall || !dma64_rxenabled(di));
-
 	i = di->rxin;
 
 	/* return if no packets posted */
@@ -1667,7 +1618,6 @@ static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall)
 
 	/* get the packet pointer that corresponds to the rx descriptor */
 	rxp = di->rxp[i];
-	ASSERT(rxp);
 	di->rxp[i] = NULL;
 
 	PHYSADDRLOSET(pa,
@@ -1709,17 +1659,13 @@ static void dma64_txrotate(dma_info_t *di)
 	u32 w;
 	u16 first, last;
 
-	ASSERT(dma64_txsuspendedidle(di));
-
 	nactive = _dma_txactive(di);
 	ad = (u16) (B2I
 		       ((((R_REG(&di->d64txregs->status1) &
 			   D64_XS1_AD_MASK)
 			  - di->xmtptrbase) & D64_XS1_AD_MASK), dma64dd_t));
 	rot = TXD(ad - di->txin);
 
-	ASSERT(rot < di->ntxd);
-
 	/* full-ring case is a lot harder - don't worry about this */
 	if (rot >= (di->ntxd - nactive)) {
 		DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
@@ -1753,7 +1699,6 @@ static void dma64_txrotate(dma_info_t *di)
 		W_SM(&di->txd64[old].addrhigh, BUS_SWAP32(0xdeadbeef));
 
 		/* move the corresponding txp[] entry */
-		ASSERT(di->txp[new] == NULL);
 		di->txp[new] = di->txp[old];
 
 		/* Move the map */
@@ -1789,7 +1734,7 @@ uint dma_addrwidth(si_t *sih, void *dmaregs)
 			     (sih->buscoretype == PCIE_CORE_ID)))
 				return DMADDRWIDTH_64;
 	}
-	ASSERT(0); /* DMA hardware not supported by this driver*/
+	/* DMA hardware not supported by this driver*/
 	return DMADDRWIDTH_64;
 }