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Mark Brown
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--- | ||
refs/heads/master: e93c7d1bc350189511d32cec2f0af79c30e7fa47 | ||
refs/heads/master: 75d8f2931a803b803cb4a850448460475c20f30b |
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CS4270 audio CODEC | ||
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The driver for this device currently only supports I2C. | ||
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Required properties: | ||
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- compatible : "cirrus,cs4270" | ||
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- reg : the I2C address of the device for I2C | ||
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Optional properties: | ||
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- reset-gpio : a GPIO spec for the reset pin. If specified, it will be | ||
deasserted before communication to the codec starts. | ||
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Example: | ||
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codec: cs4270@48 { | ||
compatible = "cirrus,cs4270"; | ||
reg = <0x48>; | ||
}; |
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44
trunk/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt
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Texas Instruments McASP controller | ||
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Required properties: | ||
- compatible : | ||
"ti,dm646x-mcasp-audio" : for DM646x platforms | ||
"ti,da830-mcasp-audio" : for both DA830 & DA850 platforms | ||
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- reg : Should contain McASP registers offset and length | ||
- interrupts : Interrupt number for McASP | ||
- op-mode : I2S/DIT ops mode. | ||
- tdm-slots : Slots for TDM operation. | ||
- num-serializer : Serializers used by McASP. | ||
- serial-dir : A list of serializer pin mode. The list number should be equal | ||
to "num-serializer" parameter. Each entry is a number indication | ||
serializer pin direction. (0 - INACTIVE, 1 - TX, 2 - RX) | ||
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Optional properties: | ||
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- ti,hwmods : Must be "mcasp<n>", n is controller instance starting 0 | ||
- tx-num-evt : FIFO levels. | ||
- rx-num-evt : FIFO levels. | ||
- sram-size-playback : size of sram to be allocated during playback | ||
- sram-size-capture : size of sram to be allocated during capture | ||
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Example: | ||
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mcasp0: mcasp0@1d00000 { | ||
compatible = "ti,da830-mcasp-audio"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
reg = <0x100000 0x3000>; | ||
interrupts = <82 83>; | ||
op-mode = <0>; /* MCASP_IIS_MODE */ | ||
tdm-slots = <2>; | ||
num-serializer = <16>; | ||
serial-dir = < | ||
0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */ | ||
0 0 0 0 | ||
0 0 0 1 | ||
2 0 0 0 >; | ||
tx-num-evt = <1>; | ||
rx-num-evt = <1>; | ||
}; |
91 changes: 91 additions & 0 deletions
91
trunk/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt
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* Texas Instruments OMAP4+ and twl6040 based audio setups | ||
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Required properties: | ||
- compatible: "ti,abe-twl6040" | ||
- ti,model: Name of the sound card ( for example "SDP4430") | ||
- ti,mclk-freq: MCLK frequency for HPPLL operation | ||
- ti,mcpdm: phandle for the McPDM node | ||
- ti,twl6040: phandle for the twl6040 core node | ||
- ti,audio-routing: List of connections between audio components. | ||
Each entry is a pair of strings, the first being the connection's sink, | ||
the second being the connection's source. | ||
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Optional properties: | ||
- ti,dmic: phandle for the OMAP dmic node if the machine have it connected | ||
- ti,jack_detection: Need to be set to <1> if the board capable to detect jack | ||
insertion, removal. | ||
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Available audio endpoints for the audio-routing table: | ||
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Board connectors: | ||
* Headset Stereophone | ||
* Earphone Spk | ||
* Ext Spk | ||
* Line Out | ||
* Vibrator | ||
* Headset Mic | ||
* Main Handset Mic | ||
* Sub Handset Mic | ||
* Line In | ||
* Digital Mic | ||
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twl6040 pins: | ||
* HSOL | ||
* HSOR | ||
* EP | ||
* HFL | ||
* HFR | ||
* AUXL | ||
* AUXR | ||
* VIBRAL | ||
* VIBRAR | ||
* HSMIC | ||
* MAINMIC | ||
* SUBMIC | ||
* AFML | ||
* AFMR | ||
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* Headset Mic Bias | ||
* Main Mic Bias | ||
* Digital Mic1 Bias | ||
* Digital Mic2 Bias | ||
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Digital mic pins: | ||
* DMic | ||
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Example: | ||
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sound { | ||
compatible = "ti,abe-twl6040"; | ||
ti,model = "SDP4430"; | ||
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ti,jack-detection = <1>; | ||
ti,mclk-freq = <38400000>; | ||
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ti,mcpdm = <&mcpdm>; | ||
ti,dmic = <&dmic>; | ||
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ti,twl6040 = <&twl6040>; | ||
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/* Audio routing */ | ||
ti,audio-routing = | ||
"Headset Stereophone", "HSOL", | ||
"Headset Stereophone", "HSOR", | ||
"Earphone Spk", "EP", | ||
"Ext Spk", "HFL", | ||
"Ext Spk", "HFR", | ||
"Line Out", "AUXL", | ||
"Line Out", "AUXR", | ||
"Vibrator", "VIBRAL", | ||
"Vibrator", "VIBRAR", | ||
"HSMIC", "Headset Mic", | ||
"Headset Mic", "Headset Mic Bias", | ||
"MAINMIC", "Main Handset Mic", | ||
"Main Handset Mic", "Main Mic Bias", | ||
"SUBMIC", "Sub Handset Mic", | ||
"Sub Handset Mic", "Main Mic Bias", | ||
"AFML", "Line In", | ||
"AFMR", "Line In", | ||
"DMic", "Digital Mic", | ||
"Digital Mic", "Digital Mic1 Bias"; | ||
}; |
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20
trunk/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
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Texas Instruments - tlv320aic3x Codec module | ||
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The tlv320aic3x serial control bus communicates through I2C protocols | ||
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Required properties: | ||
- compatible - "string" - "ti,tlv320aic3x" | ||
- reg - <int> - I2C slave address | ||
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Optional properties: | ||
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- gpio-reset - gpio pin number used for codec reset | ||
- ai3x-gpio-func - <array of 2 int> - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality | ||
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Example: | ||
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tlv320aic3x: tlv320aic3x@1b { | ||
compatible = "ti,tlv320aic3x"; | ||
reg = <0x1b>; | ||
}; |
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/* | ||
* TI DaVinci Audio definitions | ||
*/ | ||
#ifndef __ASM_ARCH_DAVINCI_ASP_H | ||
#define __ASM_ARCH_DAVINCI_ASP_H | ||
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/* Bases of dm644x and dm355 register banks */ | ||
#define DAVINCI_ASP0_BASE 0x01E02000 | ||
#define DAVINCI_ASP1_BASE 0x01E04000 | ||
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/* Bases of dm365 register banks */ | ||
#define DAVINCI_DM365_ASP0_BASE 0x01D02000 | ||
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/* Bases of dm646x register banks */ | ||
#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 | ||
#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 | ||
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/* Bases of da850/da830 McASP0 register banks */ | ||
#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 | ||
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/* Bases of da830 McASP1 register banks */ | ||
#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 | ||
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/* EDMA channels of dm644x and dm355 */ | ||
#define DAVINCI_DMA_ASP0_TX 2 | ||
#define DAVINCI_DMA_ASP0_RX 3 | ||
#define DAVINCI_DMA_ASP1_TX 8 | ||
#define DAVINCI_DMA_ASP1_RX 9 | ||
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/* EDMA channels of dm646x */ | ||
#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 | ||
#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 | ||
#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 | ||
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/* EDMA channels of da850/da830 McASP0 */ | ||
#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 | ||
#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 | ||
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/* EDMA channels of da830 McASP1 */ | ||
#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 | ||
#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 | ||
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/* Interrupts */ | ||
#define DAVINCI_ASP0_RX_INT IRQ_MBRINT | ||
#define DAVINCI_ASP0_TX_INT IRQ_MBXINT | ||
#define DAVINCI_ASP1_RX_INT IRQ_MBRINT | ||
#define DAVINCI_ASP1_TX_INT IRQ_MBXINT | ||
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#endif /* __ASM_ARCH_DAVINCI_ASP_H */ |
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