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yaml
---
r: 319599
b: refs/heads/master
c: d9831a4
h: refs/heads/master
i:
  319597: 028beb1
  319595: c8f3ca5
  319591: 1aa10cd
  319583: 0d99552
v: v3
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Florian Fainelli authored and Ralf Baechle committed Jul 23, 2012
1 parent 932e1f0 commit 652aae9
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Showing 7 changed files with 96 additions and 54 deletions.
2 changes: 1 addition & 1 deletion [refs]
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---
refs/heads/master: 6c2be5cf1d4e70e98d995f9c403b5fbe7b5f2a80
refs/heads/master: d9831a41e3409ae60e0cac353272d8ae4996b442
2 changes: 1 addition & 1 deletion trunk/arch/mips/alchemy/devboards/Makefile
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Expand Up @@ -2,7 +2,7 @@
# Alchemy Develboards
#

obj-y += bcsr.o platform.o
obj-y += prom.o bcsr.o platform.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_MIPS_PB1100) += pb1100.o
obj-$(CONFIG_MIPS_PB1500) += pb1500.o
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5 changes: 4 additions & 1 deletion trunk/arch/mips/alchemy/devboards/bcsr.c
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Expand Up @@ -90,7 +90,10 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);

disable_irq_nosync(irq);
generic_handle_irq(bcsr_csc_base + __ffs(bisr));

for ( ; bisr; bisr &= bisr - 1)
generic_handle_irq(bcsr_csc_base + __ffs(bisr));

enable_irq(irq);
}

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30 changes: 0 additions & 30 deletions trunk/arch/mips/alchemy/devboards/platform.c
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Expand Up @@ -10,39 +10,9 @@
#include <linux/platform_device.h>
#include <linux/pm.h>

#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>

#include <prom.h>

void __init prom_init(void)
{
unsigned char *memsize_str;
unsigned long memsize;

prom_argc = (int)fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;

prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
memsize = 64 << 20; /* all devboards have at least 64MB RAM */

add_memory_region(0, memsize, BOOT_MEM_RAM);
}

void prom_putchar(unsigned char c)
{
#ifdef CONFIG_MIPS_DB1300
alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
#else
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
#endif
}


static struct platform_device db1x00_rtc_dev = {
.name = "rtc-au1xxx",
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69 changes: 69 additions & 0 deletions trunk/arch/mips/alchemy/devboards/prom.c
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/*
* Common code used by all Alchemy develboards.
*
* Extracted from files which had this to say:
*
* Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/bootinfo.h>
#include <asm/mach-au1x00/au1000.h>
#include <prom.h>

#if defined(CONFIG_MIPS_DB1000) || \
defined(CONFIG_MIPS_PB1100) || \
defined(CONFIG_MIPS_PB1500)
#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000

#else /* Au1550/Au1200-based develboards */
#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x08000000
#endif

void __init prom_init(void)
{
unsigned char *memsize_str;
unsigned long memsize;

prom_argc = (int)fw_arg0;
prom_argv = (char **)fw_arg1;
prom_envp = (char **)fw_arg2;

prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE;

add_memory_region(0, memsize, BOOT_MEM_RAM);
}

void prom_putchar(unsigned char c)
{
#ifdef CONFIG_MIPS_DB1300
alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
#else
alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
#endif
}
6 changes: 3 additions & 3 deletions trunk/arch/mips/bcm63xx/clk.c
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Expand Up @@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6368())
return;
bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
CKCTL_6368_SWPKT_USB_EN |
CKCTL_6368_SWPKT_SAR_EN, enable);
if (enable) {
Expand Down Expand Up @@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, int enable)
if (BCMCPU_IS_6348())
bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
else if (BCMCPU_IS_6368())
bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
}

static struct clk clk_usbh = {
Expand Down Expand Up @@ -199,7 +199,7 @@ static void xtm_set(struct clk *clk, int enable)
if (!BCMCPU_IS_6368())
return;

bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
bcm_hwclock_set(CKCTL_6368_SAR_EN |
CKCTL_6368_SWPKT_SAR_EN, enable);

if (enable) {
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36 changes: 18 additions & 18 deletions trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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Expand Up @@ -90,29 +90,29 @@
#define CKCTL_6368_PHYMIPS_EN (1 << 6)
#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
#define CKCTL_6368_SPI_CLK_EN (1 << 9)
#define CKCTL_6368_USBD_CLK_EN (1 << 10)
#define CKCTL_6368_SAR_CLK_EN (1 << 11)
#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12)
#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13)
#define CKCTL_6368_PCM_CLK_EN (1 << 14)
#define CKCTL_6368_USBH_CLK_EN (1 << 15)
#define CKCTL_6368_SPI_EN (1 << 9)
#define CKCTL_6368_USBD_EN (1 << 10)
#define CKCTL_6368_SAR_EN (1 << 11)
#define CKCTL_6368_ROBOSW_EN (1 << 12)
#define CKCTL_6368_UTOPIA_EN (1 << 13)
#define CKCTL_6368_PCM_EN (1 << 14)
#define CKCTL_6368_USBH_EN (1 << 15)
#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
#define CKCTL_6368_NAND_CLK_EN (1 << 17)
#define CKCTL_6368_IPSEC_CLK_EN (1 << 18)
#define CKCTL_6368_NAND_EN (1 << 17)
#define CKCTL_6368_IPSEC_EN (1 << 18)

#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
CKCTL_6368_SWPKT_SAR_EN | \
CKCTL_6368_SPI_CLK_EN | \
CKCTL_6368_USBD_CLK_EN | \
CKCTL_6368_SAR_CLK_EN | \
CKCTL_6368_ROBOSW_CLK_EN | \
CKCTL_6368_UTOPIA_CLK_EN | \
CKCTL_6368_PCM_CLK_EN | \
CKCTL_6368_USBH_CLK_EN | \
CKCTL_6368_SPI_EN | \
CKCTL_6368_USBD_EN | \
CKCTL_6368_SAR_EN | \
CKCTL_6368_ROBOSW_EN | \
CKCTL_6368_UTOPIA_EN | \
CKCTL_6368_PCM_EN | \
CKCTL_6368_USBH_EN | \
CKCTL_6368_DISABLE_GLESS_EN | \
CKCTL_6368_NAND_CLK_EN | \
CKCTL_6368_IPSEC_CLK_EN)
CKCTL_6368_NAND_EN | \
CKCTL_6368_IPSEC_EN)

/* System PLL Control register */
#define PERF_SYS_PLL_CTL_REG 0x8
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