Skip to content

Commit

Permalink
ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)
Browse files Browse the repository at this point in the history
This patch is based on the
commit 1a8e41c ("ARM: 6395/1: VExpress: Set bit 22 in the PL310
(cache controller) AuxCtlr register")

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

For Zynq, this fix avoids memory inconsistencies between Gigabit
Ethernet controller (GEM) and CPU when DMA_CMA is disabled.

Suggested-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
  • Loading branch information
Thomas Betker authored and Michal Simek committed Jul 22, 2015
1 parent 974a2ab commit 6632d4f
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions arch/arm/mach-zynq/common.c
Original file line number Diff line number Diff line change
Expand Up @@ -197,8 +197,8 @@ static const char * const zynq_dt_match[] = {

DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
/* 64KB way size, 8-way associativity, parity disabled */
.l2c_aux_val = 0x00000000,
.l2c_aux_mask = 0xffffffff,
.l2c_aux_val = 0x00400000,
.l2c_aux_mask = 0xffbfffff,
.smp = smp_ops(zynq_smp_ops),
.map_io = zynq_map_io,
.init_irq = zynq_irq_init,
Expand Down

0 comments on commit 6632d4f

Please sign in to comment.