---

yaml
---
r: 20143
b: refs/heads/master
c: 7369a8b
h: refs/heads/master
i:
  20141: 7f2db50
  20139: a6a07b5
  20135: d84dccc
  20127: 0974f84
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 76a55431cc7237f018c7c667860d60e2b6427bf1
+refs/heads/master: 7369a8b39ce4be117b0f12bda4e34a1d1789dfe3

trunk/drivers/serial/dz.c

@@ -262,6 +262,7 @@ static inline void dz_receive_chars(struct dz_port *dport)
 		}
 		tty_insert_flip_char(tty, ch, flag);
 	      ignore_char:
+			;
 	} while (status & DZ_DVAL);
 
 	if (tty)

trunk/drivers/serial/ip22zilog.c

@@ -215,7 +215,7 @@ static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
 	/* Lower and upper byte of baud rate generator divisor.  */
 	write_zsreg(channel, R12, regs[R12]);
 	write_zsreg(channel, R13, regs[R13]);
-	
+
 	/* Now rewrite R14, with BRENAB (if set).  */
 	write_zsreg(channel, R14, regs[R14]);
 
@@ -571,7 +571,7 @@ static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
 	else
 		clear_bits |= DTR;
 
-	/* NOTE: Not subject to 'transmitter active' rule.  */ 
+	/* NOTE: Not subject to 'transmitter active' rule.  */
 	up->curregs[R5] |= set_bits;
 	up->curregs[R5] &= ~clear_bits;
 	write_zsreg(channel, R5, up->curregs[R5]);
@@ -654,7 +654,7 @@ static void ip22zilog_enable_ms(struct uart_port *port)
 	if (new_reg != up->curregs[R15]) {
 		up->curregs[R15] = new_reg;
 
-		/* NOTE: Not subject to 'transmitter active' rule.  */ 
+		/* NOTE: Not subject to 'transmitter active' rule.  */
 		write_zsreg(channel, R15, up->curregs[R15]);
 	}
 }
@@ -680,7 +680,7 @@ static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
 	if (new_reg != up->curregs[R5]) {
 		up->curregs[R5] = new_reg;
 
-		/* NOTE: Not subject to 'transmitter active' rule.  */ 
+		/* NOTE: Not subject to 'transmitter active' rule.  */
 		write_zsreg(channel, R5, up->curregs[R5]);
 	}