---

yaml
---
r: 130799
b: refs/heads/master
c: 476e7fa
h: refs/heads/master
i:
  130797: 4355b0e
  130795: 2b5a08d
  130791: d173870
  130783: 719f019
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 48f67f54a53bb68619a63c3f38cf7f502ed74b1d
+refs/heads/master: 476e7faefc43f106a90b5c96166c59b75de19d30

trunk/drivers/pci/pci.c

@@ -1403,19 +1403,19 @@ int pci_restore_standard_config(struct pci_dev *dev)
 	if (error)
 		return error;
 
-	if (pci_is_bridge(dev)) {
-		if (prev_state > PCI_D1)
-			mdelay(PCI_PM_BUS_WAIT);
-	} else {
-		switch(prev_state) {
-		case PCI_D3cold:
-		case PCI_D3hot:
-			mdelay(pci_pm_d3_delay);
-			break;
-		case PCI_D2:
-			udelay(PCI_PM_D2_DELAY);
-			break;
-		}
+	/*
+	 * This assumes that we won't get a bus in B2 or B3 from the BIOS, but
+	 * we've made this assumption forever and it appears to be universally
+	 * satisfied.
+	 */
+	switch(prev_state) {
+	case PCI_D3cold:
+	case PCI_D3hot:
+		mdelay(pci_pm_d3_delay);
+		break;
+	case PCI_D2:
+		udelay(PCI_PM_D2_DELAY);
+		break;
 	}
 
 	dev->current_state = PCI_D0;