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ARM: ux500: select L2X0 cache on ux500
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The cache controller needs to be enabled for the
cortex-a9 specific errata that are also selected
to work.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Arnd Bergmann authored and Linus Walleij committed Feb 29, 2012
1 parent ded547a commit 68526e5
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Expand Up @@ -8,6 +8,7 @@ config UX500_SOC_COMMON
select ARM_ERRATA_753970
select ARM_ERRATA_754322
select ARM_ERRATA_764369
select CACHE_L2X0

config UX500_SOC_DB5500
bool
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