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clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
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In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide)
instead of RATIO bit-field (4-bit wide) for dividing clock rate.

With current common clock setup, we are using RATIO bit-field which
is creating FIFO read errors while accessing eMMC. Changing over to
use PRE_RATIO bit-field fixes this issue.

dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020)
mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 1

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
CC: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Tushar Behera authored and Kukjin Kim committed Apr 8, 2013
1 parent cdbf618 commit 688f7d8
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions drivers/clk/samsung/clk-exynos5250.c
Original file line number Diff line number Diff line change
Expand Up @@ -276,10 +276,10 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 8, 8),
DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 24, 8),
DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 8, 8),
DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 24, 8),
DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
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