---

yaml
---
r: 296847
b: refs/heads/master
c: 3f8349e
h: refs/heads/master
i:
  296845: 8d15786
  296843: 6131ea2
  296839: 12cffe1
  296831: 9a955b4
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 91d6a9a6c0d98ef6daeaf229e5acada652b4f6f0
+refs/heads/master: 3f8349e6e98ba0455437724589072523865eae5e

trunk/drivers/mfd/twl6030-irq.c

@@ -185,8 +185,17 @@ static int twl6030_irq_thread(void *data)
 			}
 		local_irq_enable();
 		}
-		ret = twl_i2c_write(TWL_MODULE_PIH, sts.bytes,
-				REG_INT_STS_A, 3); /* clear INT_STS_A */
+
+		/*
+		 * NOTE:
+		 * Simulation confirms that documentation is wrong w.r.t the
+		 * interrupt status clear operation. A single *byte* write to
+		 * any one of STS_A to STS_C register results in all three
+		 * STS registers being reset. Since it does not matter which
+		 * value is written, all three registers are cleared on a
+		 * single byte write, so we just use 0x0 to clear.
+		 */
+		ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
 		if (ret)
 			pr_warning("twl6030: I2C error in clearing PIH ISR\n");