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---
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yaml
---
r: 258318
b: refs/heads/master
c: f4daf06
h: refs/heads/master
v: v3
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Will Deacon committed Jul 7, 2011
1 parent e0e0f18 commit 6c5fd2f
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Showing 3 changed files with 13 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 14abd038a7a209193c58ee7dde01ef4bf1523a91
refs/heads/master: f4daf06fc23b99df5ca5b3e892428b91e148cc52
5 changes: 5 additions & 0 deletions trunk/arch/arm/mm/proc-v6.S
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,11 @@ ENTRY(cpu_v6_proc_fin)
*/
.align 5
ENTRY(cpu_v6_reset)
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x1 @ ...............m
mcr p15, 0, r1, c1, c0, 0 @ disable MMU
mov r1, #0
mcr p15, 0, r1, c7, c5, 4 @ ISB
mov pc, r0

/*
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7 changes: 7 additions & 0 deletions trunk/arch/arm/mm/proc-v7.S
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Expand Up @@ -58,9 +58,16 @@ ENDPROC(cpu_v7_proc_fin)
* to what would be the reset vector.
*
* - loc - location to jump to for soft reset
*
* This code must be executed using a flat identity mapping with
* caches disabled.
*/
.align 5
ENTRY(cpu_v7_reset)
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x1 @ ...............m
mcr p15, 0, r1, c1, c0, 0 @ disable MMU
isb
mov pc, r0
ENDPROC(cpu_v7_reset)

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