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Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/k…
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…ernel/git/jgarzik/libata-dev

* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: (21 commits)
  libata: bump transfer chunk size if it's odd
  libata: Return proper ATA INT status in pata_bf54x driver
  pata_ali: trim trailing whitespace (fix checkpatch complaints)
  pata_isapnp: Polled devices
  pata_hpt37x: Fix cable detect bug spotted by Sergei
  pata_ali: Lots of problems still showing up with small ATAPI DMA
  pata_ali: Add Mitac 8317 and derivatives
  libata-core: List more documentation sources for reference
  ata_piix: Invalid use of writel/readl with iomap
  sata_sil24: fix sg table sizing
  pata_jmicron: fix disabled port handling in jmicron_pre_reset()
  pata_sil680: kill bogus reset code (take 2)
  ata_piix: port enable for the first SATA controller of ICH8 is 0xf not 0x3
  ata_piix: only enable the first port on apple macbook pro
  ata_piix: reorganize controller IDs
  pata_sis.c: Add Packard Bell EasyNote K5305 to laptops
  libata-scsi: be tolerant of 12-byte ATAPI commands in 16-byte CDBs
  libata: use ATA_HORKAGE_STUCK_ERR for ATAPI tape drives
  libata: workaround DRQ=1 ERR=1 for ATAPI tape drives
  libata: remove unused functions
  ...
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Linus Torvalds committed Nov 27, 2007
2 parents f4d53ce + e190222 commit 6d27294
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Showing 13 changed files with 184 additions and 262 deletions.
93 changes: 64 additions & 29 deletions drivers/ata/ata_piix.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -119,18 +119,19 @@ enum {
PIIX_80C_SEC = (1 << 7) | (1 << 6),

/* controller IDs */
piix_pata_33 = 0, /* PIIX4 at 33Mhz */
ich_pata_33 = 1, /* ICH up to UDMA 33 only */
ich_pata_66 = 2, /* ICH up to 66 Mhz */
ich_pata_100 = 3, /* ICH up to UDMA 100 */
ich5_sata = 5,
ich6_sata = 6,
ich6_sata_ahci = 7,
ich6m_sata_ahci = 8,
ich8_sata_ahci = 9,
piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
tolapai_sata_ahci = 11,
ich9_2port_sata = 12,
piix_pata_mwdma = 0, /* PIIX3 MWDMA only */
piix_pata_33, /* PIIX4 at 33Mhz */
ich_pata_33, /* ICH up to UDMA 33 only */
ich_pata_66, /* ICH up to 66 Mhz */
ich_pata_100, /* ICH up to UDMA 100 */
ich5_sata,
ich6_sata,
ich6_sata_ahci,
ich6m_sata_ahci,
ich8_sata_ahci,
ich8_2port_sata,
ich8m_apple_sata_ahci, /* locks up on second port enable */
tolapai_sata_ahci,

/* constants for mapping table */
P0 = 0, /* port 0 */
Expand Down Expand Up @@ -239,19 +240,21 @@ static const struct pci_device_id piix_pci_tbl[] = {
/* SATA Controller 1 IDE (ICH8) */
{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* SATA Controller 2 IDE (ICH8) */
{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* Mobile SATA Controller IDE (ICH8M) */
{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* Mobile SATA Controller IDE (ICH8M), Apple */
{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
/* SATA Controller IDE (ICH9) */
{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* SATA Controller IDE (ICH9) */
{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* SATA Controller IDE (ICH9) */
{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* SATA Controller IDE (ICH9M) */
{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* SATA Controller IDE (ICH9M) */
{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
/* SATA Controller IDE (ICH9M) */
{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
/* SATA Controller IDE (Tolapai) */
Expand Down Expand Up @@ -427,7 +430,7 @@ static const struct piix_map_db ich6m_map_db = {

static const struct piix_map_db ich8_map_db = {
.mask = 0x3,
.port_enable = 0x3,
.port_enable = 0xf,
.map = {
/* PM PS SM SS MAP */
{ P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
Expand All @@ -437,7 +440,7 @@ static const struct piix_map_db ich8_map_db = {
},
};

static const struct piix_map_db tolapai_map_db = {
static const struct piix_map_db ich8_2port_map_db = {
.mask = 0x3,
.port_enable = 0x3,
.map = {
Expand All @@ -449,7 +452,19 @@ static const struct piix_map_db tolapai_map_db = {
},
};

static const struct piix_map_db ich9_2port_map_db = {
static const struct piix_map_db ich8m_apple_map_db = {
.mask = 0x3,
.port_enable = 0x1,
.map = {
/* PM PS SM SS MAP */
{ P0, NA, NA, NA }, /* 00b */
{ RV, RV, RV, RV },
{ P0, P2, IDE, IDE }, /* 10b */
{ RV, RV, RV, RV },
},
};

static const struct piix_map_db tolapai_map_db = {
.mask = 0x3,
.port_enable = 0x3,
.map = {
Expand All @@ -467,11 +482,21 @@ static const struct piix_map_db *piix_map_db_table[] = {
[ich6_sata_ahci] = &ich6_map_db,
[ich6m_sata_ahci] = &ich6m_map_db,
[ich8_sata_ahci] = &ich8_map_db,
[ich8_2port_sata] = &ich8_2port_map_db,
[ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
[tolapai_sata_ahci] = &tolapai_map_db,
[ich9_2port_sata] = &ich9_2port_map_db,
};

static struct ata_port_info piix_port_info[] = {
[piix_pata_mwdma] = /* PIIX3 MWDMA only */
{
.sht = &piix_sht,
.flags = PIIX_PATA_FLAGS,
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
.port_ops = &piix_pata_ops,
},

[piix_pata_33] = /* PIIX4 at 33MHz */
{
.sht = &piix_sht,
Expand Down Expand Up @@ -565,13 +590,15 @@ static struct ata_port_info piix_port_info[] = {
.port_ops = &piix_sata_ops,
},

[piix_pata_mwdma] = /* PIIX3 MWDMA only */
[ich8_2port_sata] =
{
.sht = &piix_sht,
.flags = PIIX_PATA_FLAGS,
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
PIIX_FLAG_AHCI,
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
.port_ops = &piix_pata_ops,
.mwdma_mask = 0x07, /* mwdma0-2 */
.udma_mask = ATA_UDMA6,
.port_ops = &piix_sata_ops,
},

[tolapai_sata_ahci] =
Expand All @@ -585,7 +612,7 @@ static struct ata_port_info piix_port_info[] = {
.port_ops = &piix_sata_ops,
},

[ich9_2port_sata] =
[ich8m_apple_sata_ahci] =
{
.sht = &piix_sht,
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
Expand All @@ -595,6 +622,7 @@ static struct ata_port_info piix_port_info[] = {
.udma_mask = ATA_UDMA6,
.port_ops = &piix_sata_ops,
},

};

static struct pci_bits piix_enable_bits[] = {
Expand Down Expand Up @@ -973,6 +1001,13 @@ static int piix_broken_suspend(void)
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
},
},
{
.ident = "SATELLITE U205",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
},
},
{
.ident = "Portege M500",
.matches = {
Expand Down Expand Up @@ -1086,12 +1121,12 @@ static int piix_disable_ahci(struct pci_dev *pdev)
if (!mmio)
return -ENOMEM;

tmp = readl(mmio + AHCI_GLOBAL_CTL);
tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
if (tmp & AHCI_ENABLE) {
tmp &= ~AHCI_ENABLE;
writel(tmp, mmio + AHCI_GLOBAL_CTL);
iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);

tmp = readl(mmio + AHCI_GLOBAL_CTL);
tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
if (tmp & AHCI_ENABLE)
rc = -EIO;
}
Expand Down
108 changes: 24 additions & 84 deletions drivers/ata/libata-core.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,14 @@
* Hardware documentation available from http://www.t13.org/ and
* http://www.sata-io.org/
*
* Standards documents from:
* http://www.t13.org (ATA standards, PCI DMA IDE spec)
* http://www.t10.org (SCSI MMC - for ATAPI MMC)
* http://www.sata-io.org (SATA)
* http://www.compactflash.org (CF)
* http://www.qic.org (QIC157 - Tape and DSC)
* http://www.ce-ata.org (CE-ATA: not supported)
*
*/

#include <linux/kernel.h>
Expand Down Expand Up @@ -2307,8 +2315,10 @@ int ata_dev_configure(struct ata_device *dev)
}

if ((dev->class == ATA_DEV_ATAPI) &&
(atapi_command_packet_set(id) == TYPE_TAPE))
(atapi_command_packet_set(id) == TYPE_TAPE)) {
dev->max_sectors = ATA_MAX_SECTORS_TAPE;
dev->horkage |= ATA_HORKAGE_STUCK_ERR;
}

if (dev->horkage & ATA_HORKAGE_MAX_SEC_128)
dev->max_sectors = min_t(unsigned int, ATA_MAX_SECTORS_128,
Expand Down Expand Up @@ -2580,81 +2590,6 @@ void sata_print_link_status(struct ata_link *link)
}
}

/**
* __sata_phy_reset - Wake/reset a low-level SATA PHY
* @ap: SATA port associated with target SATA PHY.
*
* This function issues commands to standard SATA Sxxx
* PHY registers, to wake up the phy (and device), and
* clear any reset condition.
*
* LOCKING:
* PCI/etc. bus probe sem.
*
*/
void __sata_phy_reset(struct ata_port *ap)
{
struct ata_link *link = &ap->link;
unsigned long timeout = jiffies + (HZ * 5);
u32 sstatus;

if (ap->flags & ATA_FLAG_SATA_RESET) {
/* issue phy wake/reset */
sata_scr_write_flush(link, SCR_CONTROL, 0x301);
/* Couldn't find anything in SATA I/II specs, but
* AHCI-1.1 10.4.2 says at least 1 ms. */
mdelay(1);
}
/* phy wake/clear reset */
sata_scr_write_flush(link, SCR_CONTROL, 0x300);

/* wait for phy to become ready, if necessary */
do {
msleep(200);
sata_scr_read(link, SCR_STATUS, &sstatus);
if ((sstatus & 0xf) != 1)
break;
} while (time_before(jiffies, timeout));

/* print link status */
sata_print_link_status(link);

/* TODO: phy layer with polling, timeouts, etc. */
if (!ata_link_offline(link))
ata_port_probe(ap);
else
ata_port_disable(ap);

if (ap->flags & ATA_FLAG_DISABLED)
return;

if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
ata_port_disable(ap);
return;
}

ap->cbl = ATA_CBL_SATA;
}

/**
* sata_phy_reset - Reset SATA bus.
* @ap: SATA port associated with target SATA PHY.
*
* This function resets the SATA bus, and then probes
* the bus for devices.
*
* LOCKING:
* PCI/etc. bus probe sem.
*
*/
void sata_phy_reset(struct ata_port *ap)
{
__sata_phy_reset(ap);
if (ap->flags & ATA_FLAG_DISABLED)
return;
ata_bus_reset(ap);
}

/**
* ata_dev_pair - return other device on cable
* @adev: device
Expand Down Expand Up @@ -5490,11 +5425,19 @@ int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
* let the EH abort the command or reset the device.
*/
if (unlikely(status & (ATA_ERR | ATA_DF))) {
ata_port_printk(ap, KERN_WARNING, "DRQ=1 with device "
"error, dev_stat 0x%X\n", status);
qc->err_mask |= AC_ERR_HSM;
ap->hsm_task_state = HSM_ST_ERR;
goto fsm_start;
/* Some ATAPI tape drives forget to clear the ERR bit
* when doing the next command (mostly request sense).
* We ignore ERR here to workaround and proceed sending
* the CDB.
*/
if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
ata_port_printk(ap, KERN_WARNING,
"DRQ=1 with device error, "
"dev_stat 0x%X\n", status);
qc->err_mask |= AC_ERR_HSM;
ap->hsm_task_state = HSM_ST_ERR;
goto fsm_start;
}
}

/* Send the CDB (atapi) or the first data block (ata pio out).
Expand Down Expand Up @@ -7653,8 +7596,6 @@ EXPORT_SYMBOL_GPL(ata_dev_disable);
EXPORT_SYMBOL_GPL(sata_set_spd);
EXPORT_SYMBOL_GPL(sata_link_debounce);
EXPORT_SYMBOL_GPL(sata_link_resume);
EXPORT_SYMBOL_GPL(sata_phy_reset);
EXPORT_SYMBOL_GPL(__sata_phy_reset);
EXPORT_SYMBOL_GPL(ata_bus_reset);
EXPORT_SYMBOL_GPL(ata_std_prereset);
EXPORT_SYMBOL_GPL(ata_std_softreset);
Expand Down Expand Up @@ -7725,7 +7666,6 @@ EXPORT_SYMBOL_GPL(ata_port_desc);
#ifdef CONFIG_PCI
EXPORT_SYMBOL_GPL(ata_port_pbar_desc);
#endif /* CONFIG_PCI */
EXPORT_SYMBOL_GPL(ata_eng_timeout);
EXPORT_SYMBOL_GPL(ata_port_schedule_eh);
EXPORT_SYMBOL_GPL(ata_link_abort);
EXPORT_SYMBOL_GPL(ata_port_abort);
Expand Down
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