---

yaml --- r: 221095 b: refs/heads/master c: 4b46fbb h: refs/heads/master i: 221093: 0862f65 221091: f4a090f 221087: 32e8b68 v: v3
git-mirror · Oct 23, 2010 · 6e387ca · 6e387ca
1 parent 382af48
commit 6e387ca
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Showing 55 changed files with 504 additions and 2,274 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: dc6c0ca39daad44f3169656296ef81d39a6dc7f5
+refs/heads/master: 4b46fbba607ef99f1aab3b77bfc1dc25464df5a6
diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig
@@ -717,7 +717,6 @@ config ARCH_S5PC100
 config ARCH_S5PV210
 	bool "Samsung S5PV210/S5PC110"
 	select CPU_V7
-	select ARCH_SPARSEMEM_ENABLE
 	select GENERIC_GPIO
 	select HAVE_CLK
 	select ARM_L1_CACHE_SHIFT_6
@@ -731,12 +730,9 @@ config ARCH_S5PV210
 config ARCH_S5PV310
 	bool "Samsung S5PV310/S5PC210"
 	select CPU_V7
-	select ARCH_SPARSEMEM_ENABLE
 	select GENERIC_GPIO
 	select HAVE_CLK
 	select GENERIC_CLOCKEVENTS
-	select HAVE_S3C_RTC
-	select HAVE_S3C2410_WATCHDOG
 	help
 	  Samsung S5PV310 series based systems
 

diff --git a/trunk/arch/arm/mach-s3c64xx/gpiolib.c b/trunk/arch/arm/mach-s3c64xx/gpiolib.c
@@ -195,6 +195,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
 	.get_pull	= s3c_gpio_getpull_updown,
 };
 
+int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
+{
+	return IRQ_EINT(0) + pin;
+}
+
 static struct s3c_gpio_chip gpio_2bit[] = {
 	{
 		.base	= S3C64XX_GPF_BASE,
@@ -222,13 +227,12 @@ static struct s3c_gpio_chip gpio_2bit[] = {
 		},
 	}, {
 		.base	= S3C64XX_GPN_BASE,
-		.irq_base = IRQ_EINT(0),
 		.config	= &gpio_2bit_cfg_eint10,
 		.chip	= {
 			.base	= S3C64XX_GPN(0),
 			.ngpio	= S3C64XX_GPIO_N_NR,
 			.label	= "GPN",
-			.to_irq = samsung_gpiolib_to_irq,
+			.to_irq = s3c64xx_gpio2int_gpn,
 		},
 	}, {
 		.base	= S3C64XX_GPO_BASE,

diff --git a/trunk/arch/arm/mach-s5p6442/Kconfig b/trunk/arch/arm/mach-s5p6442/Kconfig
@@ -11,6 +11,7 @@ if ARCH_S5P6442
 
 config CPU_S5P6442
 	bool
+	select PLAT_S5P
 	select S3C_PL330_DMA
 	help
 	  Enable S5P6442 CPU support

diff --git a/trunk/arch/arm/mach-s5p64x0/Kconfig b/trunk/arch/arm/mach-s5p64x0/Kconfig
@@ -9,12 +9,14 @@ if ARCH_S5P64X0
 
 config CPU_S5P6440
 	bool
+	select PLAT_S5P
 	select S3C_PL330_DMA
 	help
 	  Enable S5P6440 CPU support
 
 config CPU_S5P6450
 	bool
+	select PLAT_S5P
 	select S3C_PL330_DMA
 	help
 	  Enable S5P6450 CPU support

diff --git a/trunk/arch/arm/mach-s5pc100/Kconfig b/trunk/arch/arm/mach-s5pc100/Kconfig
@@ -9,6 +9,7 @@ if ARCH_S5PC100
 
 config CPU_S5PC100
 	bool
+	select PLAT_S5P
 	select S5P_EXT_INT
 	select S3C_PL330_DMA
 	help

diff --git a/trunk/arch/arm/mach-s5pc100/Makefile b/trunk/arch/arm/mach-s5pc100/Makefile
@@ -11,7 +11,7 @@ obj-				:=
 
 # Core support for S5PC100 system
 
-obj-$(CONFIG_CPU_S5PC100)	+= cpu.o init.o clock.o gpiolib.o
+obj-$(CONFIG_CPU_S5PC100)	+= cpu.o init.o clock.o gpiolib.o irq-gpio.o
 obj-$(CONFIG_CPU_S5PC100)	+= setup-i2c0.o
 obj-$(CONFIG_CPU_S5PC100)	+= dma.o
 

diff --git a/trunk/arch/arm/mach-s5pc100/gpiolib.c b/trunk/arch/arm/mach-s5pc100/gpiolib.c
@@ -61,6 +61,30 @@
  * L3	8	4Bit	None
  */
 
+static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	return S3C_IRQ_GPIO(chip->base + offset);
+}
+
+static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
+{
+	int base;
+
+	base = chip->base - S5PC100_GPH0(0);
+	if (base == 0)
+		return IRQ_EINT(offset);
+	base = chip->base - S5PC100_GPH1(0);
+	if (base == 0)
+		return IRQ_EINT(8 + offset);
+	base = chip->base - S5PC100_GPH2(0);
+	if (base == 0)
+		return IRQ_EINT(16 + offset);
+	base = chip->base - S5PC100_GPH3(0);
+	if (base == 0)
+		return IRQ_EINT(24 + offset);
+	return -EINVAL;
+}
+
 static struct s3c_gpio_cfg gpio_cfg = {
 	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
 	.set_pull	= s3c_gpio_setpull_updown,
@@ -204,42 +228,34 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 	}, {
 		.base	= S5PC100_GPH0_BASE,
 		.config	= &gpio_cfg_eint,
-		.irq_base = IRQ_EINT(0),
 		.chip	= {
 			.base	= S5PC100_GPH0(0),
 			.ngpio	= S5PC100_GPIO_H0_NR,
 			.label	= "GPH0",
-			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH1_BASE,
 		.config	= &gpio_cfg_eint,
-		.irq_base = IRQ_EINT(8),
 		.chip	= {
 			.base	= S5PC100_GPH1(0),
 			.ngpio	= S5PC100_GPIO_H1_NR,
 			.label	= "GPH1",
-			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH2_BASE,
 		.config	= &gpio_cfg_eint,
-		.irq_base = IRQ_EINT(16),
 		.chip	= {
 			.base	= S5PC100_GPH2(0),
 			.ngpio	= S5PC100_GPIO_H2_NR,
 			.label	= "GPH2",
-			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH3_BASE,
 		.config	= &gpio_cfg_eint,
-		.irq_base = IRQ_EINT(24),
 		.chip	= {
 			.base	= S5PC100_GPH3(0),
 			.ngpio	= S5PC100_GPIO_H3_NR,
 			.label	= "GPH3",
-			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPI_BASE,
@@ -364,25 +380,47 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 	},
 };
 
+/* FIXME move from irq-gpio.c */
+extern struct irq_chip s5pc100_gpioint;
+extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
+
+static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
+{
+	/* Interrupt */
+	if (chip->config == &gpio_cfg) {
+		int i, irq;
+
+		chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+
+		for (i = 0;  i < chip->chip.ngpio; i++) {
+			irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
+			set_irq_chip(irq, &s5pc100_gpioint);
+			set_irq_data(irq, &chip->chip);
+			set_irq_handler(irq, handle_level_irq);
+			set_irq_flags(irq, IRQF_VALID);
+		}
+	} else if (chip->config == &gpio_cfg_eint) {
+		chip->chip.to_irq = s5pc100_gpiolib_to_eint;
+	}
+}
+
 static __init int s5pc100_gpiolib_init(void)
 {
 	struct s3c_gpio_chip *chip;
 	int nr_chips;
-	int gpioint_group = 0;
 
 	chip = s5pc100_gpio_chips;
 	nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
 
-	for (; nr_chips > 0; nr_chips--, chip++) {
-		if (chip->config == &gpio_cfg) {
-			/* gpio interrupts */
-			chip->group = gpioint_group++;
-		}
-	}
+	for (; nr_chips > 0; nr_chips--, chip++)
+		s5pc100_gpiolib_link(chip);
 
 	samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
 				       ARRAY_SIZE(s5pc100_gpio_chips));
 
+	/* Interrupt */
+	set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
+
 	return 0;
 }
 core_initcall(s5pc100_gpiolib_init);
diff --git a/trunk/arch/arm/mach-s5pc100/include/mach/gpio.h b/trunk/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,6 +146,13 @@ enum s5p_gpio_number {
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS		(S5PC100_GPIO_END + 1)
 
+#define EINT_MODE		S3C_GPIO_SFN(0x2)
+
+#define EINT_GPIO_0(x)		S5PC100_GPH0(x)
+#define EINT_GPIO_1(x)		S5PC100_GPH1(x)
+#define EINT_GPIO_2(x)		S5PC100_GPH2(x)
+#define EINT_GPIO_3(x)		S5PC100_GPH3(x)
+
 #include <asm-generic/gpio.h>
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/trunk/arch/arm/mach-s5pc100/include/mach/irqs.h b/trunk/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -100,12 +100,11 @@
 #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
 
-/* GPIO interrupt */
-#define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
-#define S5P_GPIOINT_GROUP_MAXNR	21
+#define S3C_IRQ_GPIO_BASE	(IRQ_EINT(31) + 1)
+#define S3C_IRQ_GPIO(x)		(S3C_IRQ_GPIO_BASE + (x))
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
+#define NR_IRQS		(S3C_IRQ_GPIO(320) + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

diff --git a/trunk/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/trunk/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -64,12 +64,12 @@
 
 #define eint_irq_to_bit(irq)		(1 << (EINT_OFFSET(irq) & 0x7))
 
-#define EINT_MODE		S3C_GPIO_SFN(0x2)
-
-#define EINT_GPIO_0(x)		S5PC100_GPH0(x)
-#define EINT_GPIO_1(x)		S5PC100_GPH1(x)
-#define EINT_GPIO_2(x)		S5PC100_GPH2(x)
-#define EINT_GPIO_3(x)		S5PC100_GPH3(x)
+/* values for S5P_EXTINT0 */
+#define S5P_EXTINT_LOWLEV		(0x00)
+#define S5P_EXTINT_HILEV		(0x01)
+#define S5P_EXTINT_FALLEDGE		(0x02)
+#define S5P_EXTINT_RISEEDGE		(0x03)
+#define S5P_EXTINT_BOTHEDGE		(0x04)
 
 #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */