---

yaml --- r: 21351 b: refs/heads/master c: a8b900d h: refs/heads/master i: 21349: 05e4fad 21347: efb840c 21343: 0d269c4 v: v3
git-mirror · Mar 20, 2006 · 6eb16b7 · 6eb16b7
1 parent e0effca
commit 6eb16b7
Show file tree

Hide file tree

Showing 4 changed files with 5 additions and 11 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3487d1d4414fbfab5d98ec559e6f84f55520cb15
+refs/heads/master: a8b900d801697609d1b56cc9c110148c64678068
diff --git a/trunk/arch/sparc64/kernel/head.S b/trunk/arch/sparc64/kernel/head.S
@@ -454,7 +454,7 @@ setup_trap_table:
 	 restore
 
 	.globl	setup_tba
-setup_tba:	/* i0 = is_starfire */
+setup_tba:
 	save	%sp, -192, %sp
 
 	/* The boot processor is the only cpu which invokes this

diff --git a/trunk/arch/sparc64/mm/init.c b/trunk/arch/sparc64/mm/init.c
@@ -1092,15 +1092,8 @@ void __init paging_init(void)
 
 	inherit_prom_mappings();
 
-	/* Ok, we can use our TLB miss and window trap handlers safely.
-	 * We need to do a quick peek here to see if we are on StarFire
-	 * or not, so setup_tba can setup the IRQ globals correctly (it
-	 * needs to get the hard smp processor id correctly).
-	 */
-	{
-		extern void setup_tba(int);
-		setup_tba(this_is_starfire);
-	}
+	/* Ok, we can use our TLB miss and window trap handlers safely.  */
+	setup_tba();
 
 	__flush_tlb_all();
 

diff --git a/trunk/include/asm-sparc64/cpudata.h b/trunk/include/asm-sparc64/cpudata.h
@@ -61,6 +61,7 @@ struct trap_per_cpu {
 extern struct trap_per_cpu trap_block[NR_CPUS];
 extern void init_cur_cpu_trap(void);
 extern void per_cpu_patch(void);
+extern void setup_tba(void);
 
 #endif /* !(__ASSEMBLY__) */