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Documentation: clk: Fix a trivial typo in audss
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Fixes a trivial typo.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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Sachin Kamat authored and Mike Turquette committed Aug 8, 2013
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
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The Samsung Audio Subsystem clock controller generates and supplies clocks
to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
binding described here is applicable to all SoC's in Exynos family.
binding described here is applicable to all SoCs in Exynos family.

Required Properties:

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