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yaml --- r: 113119 b: refs/heads/master c: a21cff3 h: refs/heads/master i: 113117: 12955d6 113115: 16d5719 113111: fe4083e 113103: 866acb2 113087: ba797fa v: v3
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David S. Miller
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Sep 11, 2008
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refs/heads/master: 22fecbae4446ad470b9237ee9b79f80f343b3838 | ||
refs/heads/master: a21cff3e5e39c087b5a4c5efb20f1744475c556e |
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/* psycho_common.c: Code common to PSYCHO and derivative PCI controllers. | ||
* | ||
* Copyright (C) 2008 David S. Miller <davem@davemloft.net> | ||
*/ | ||
#include <linux/kernel.h> | ||
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#include <asm/upa.h> | ||
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#include "pci_impl.h" | ||
#include "psycho_common.h" | ||
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#define PSYCHO_IOMMU_TAG 0xa580UL | ||
#define PSYCHO_IOMMU_DATA 0xa600UL | ||
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static void psycho_iommu_flush(struct pci_pbm_info *pbm) | ||
{ | ||
int i; | ||
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for (i = 0; i < 16; i++) { | ||
unsigned long off = i * 8; | ||
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upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_TAG + off); | ||
upa_writeq(0, pbm->controller_regs + PSYCHO_IOMMU_DATA + off); | ||
} | ||
} | ||
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#define PSYCHO_IOMMU_CONTROL 0x0200UL | ||
#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL | ||
#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL | ||
#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL | ||
#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL | ||
#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL | ||
#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL | ||
#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL | ||
#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL | ||
#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL | ||
#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL | ||
#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL | ||
#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL | ||
#define PSYCHO_IOMMU_FLUSH 0x0210UL | ||
#define PSYCHO_IOMMU_TSBBASE 0x0208UL | ||
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int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize, | ||
u32 dvma_offset, u32 dma_mask, | ||
unsigned long write_complete_offset) | ||
{ | ||
struct iommu *iommu = pbm->iommu; | ||
u64 control; | ||
int err; | ||
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iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL; | ||
iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE; | ||
iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH; | ||
iommu->iommu_tags = pbm->controller_regs + PSYCHO_IOMMU_TAG; | ||
iommu->write_complete_reg = (pbm->controller_regs + | ||
write_complete_offset); | ||
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iommu->iommu_ctxflush = 0; | ||
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control = upa_readq(iommu->iommu_control); | ||
control |= PSYCHO_IOMMU_CTRL_DENAB; | ||
upa_writeq(control, iommu->iommu_control); | ||
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psycho_iommu_flush(pbm); | ||
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/* Leave diag mode enabled for full-flushing done in pci_iommu.c */ | ||
err = iommu_table_init(iommu, tsbsize * 1024 * 8, | ||
dvma_offset, dma_mask, pbm->numa_node); | ||
if (err) | ||
return err; | ||
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upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); | ||
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control = upa_readq(iommu->iommu_control); | ||
control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ); | ||
control |= PSYCHO_IOMMU_CTRL_ENAB; | ||
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switch (tsbsize) { | ||
case 64: | ||
control |= PSYCHO_IOMMU_TSBSZ_64K; | ||
break; | ||
case 128: | ||
control |= PSYCHO_IOMMU_TSBSZ_128K; | ||
break; | ||
default: | ||
return -EINVAL; | ||
} | ||
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upa_writeq(control, iommu->iommu_control); | ||
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return 0; | ||
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} |
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#ifndef _PSYCHO_COMMON_H | ||
#define _PSYCHO_COMMON_H | ||
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extern int psycho_iommu_init(struct pci_pbm_info *pbm, int tsbsize, | ||
u32 dvma_offset, u32 dma_mask, | ||
unsigned long write_complete_offset); | ||
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#endif /* _PSYCHO_COMMON_H */ |