Skip to content

Commit

Permalink
sh: dma-sh updates for multi IRQ and new SH-4A CPUs.
Browse files Browse the repository at this point in the history 
This adds DMA support for newer SH-4A CPUs, particularly SH7763/64/80/85.

This also enables multi IRQ support for platforms that have multiple
vectors bound to the same IRQ source.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
  • Loading branch information
Nobuhiro Iwamatsu authored and Paul Mundt committed Mar 10, 2009
1 parent ae68df5 commit 71b973a
Show file tree
Hide file tree
Showing 9 changed files with 352 additions and 204 deletions.
8 changes: 4 additions & 4 deletions arch/sh/drivers/dma/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,10 @@ config SH_DMA
config NR_ONCHIP_DMA_CHANNELS
int
depends on SH_DMA
default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
default "12" if CPU_SUBTYPE_SH7780
default "4"
default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7750S
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7760
default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
default "6"
help
This allows you to specify the number of channels that the on-chip
DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the
Expand Down
172 changes: 115 additions & 57 deletions arch/sh/drivers/dma/dma-sh.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,36 +17,38 @@
#include <mach-dreamcast/mach/dma.h>
#include <asm/dma.h>
#include <asm/io.h>
#include "dma-sh.h"

static int dmte_irq_map[] = {
DMTE0_IRQ,
DMTE1_IRQ,
DMTE2_IRQ,
DMTE3_IRQ,
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
defined(CONFIG_CPU_SUBTYPE_SH7760) || \
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
DMTE4_IRQ,
DMTE5_IRQ,
#include <asm/dma-sh.h>

#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7764) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
#define DMAC_IRQ_MULTI 1
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
defined(CONFIG_CPU_SUBTYPE_SH7760) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
DMTE6_IRQ,
DMTE7_IRQ,

#if defined(DMAE1_IRQ)
#define NR_DMAE 2
#else
#define NR_DMAE 1
#endif

static const char *dmae_name[] = {
"DMAC Address Error0", "DMAC Address Error1"
};

static inline unsigned int get_dmte_irq(unsigned int chan)
{
unsigned int irq = 0;
if (chan < ARRAY_SIZE(dmte_irq_map))
irq = dmte_irq_map[chan];

#if defined(DMAC_IRQ_MULTI)
if (irq > DMTE6_IRQ)
return DMTE6_IRQ;
return DMTE0_IRQ;
#else
return irq;
#endif
}

/*
Expand All @@ -59,7 +61,7 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
*/
static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
{
u32 chcr = ctrl_inl(CHCR[chan->chan]);
u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);

return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
}
Expand All @@ -75,13 +77,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
struct dma_channel *chan = dev_id;
u32 chcr;

chcr = ctrl_inl(CHCR[chan->chan]);
chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);

if (!(chcr & CHCR_TE))
return IRQ_NONE;

chcr &= ~(CHCR_IE | CHCR_DE);
ctrl_outl(chcr, CHCR[chan->chan]);
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));

wake_up(&chan->wait_queue);

Expand All @@ -94,7 +96,12 @@ static int sh_dmac_request_dma(struct dma_channel *chan)
return 0;

return request_irq(get_dmte_irq(chan->chan), dma_tei,
IRQF_DISABLED, chan->dev_id, chan);
#if defined(DMAC_IRQ_MULTI)
IRQF_SHARED,
#else
IRQF_DISABLED,
#endif
chan->dev_id, chan);
}

static void sh_dmac_free_dma(struct dma_channel *chan)
Expand All @@ -115,7 +122,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
chan->flags &= ~DMA_TEI_CAPABLE;
}

ctrl_outl(chcr, CHCR[chan->chan]);
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));

chan->flags |= DMA_CONFIGURED;
return 0;
Expand All @@ -126,13 +133,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
int irq;
u32 chcr;

chcr = ctrl_inl(CHCR[chan->chan]);
chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
chcr |= CHCR_DE;

if (chan->flags & DMA_TEI_CAPABLE)
chcr |= CHCR_IE;

ctrl_outl(chcr, CHCR[chan->chan]);
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));

if (chan->flags & DMA_TEI_CAPABLE) {
irq = get_dmte_irq(chan->chan);
Expand All @@ -150,9 +157,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
disable_irq(irq);
}

chcr = ctrl_inl(CHCR[chan->chan]);
chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
ctrl_outl(chcr, CHCR[chan->chan]);
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
}

static int sh_dmac_xfer_dma(struct dma_channel *chan)
Expand Down Expand Up @@ -183,12 +190,13 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
*/
if (chan->sar || (mach_is_dreamcast() &&
chan->chan == PVR2_CASCADE_CHAN))
ctrl_outl(chan->sar, SAR[chan->chan]);
ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR));
if (chan->dar || (mach_is_dreamcast() &&
chan->chan == PVR2_CASCADE_CHAN))
ctrl_outl(chan->dar, DAR[chan->chan]);
ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR));

ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
ctrl_outl(chan->count >> calc_xmit_shift(chan),
(dma_base_addr[chan->chan] + TCR));

sh_dmac_enable_dma(chan);

Expand All @@ -197,36 +205,26 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)

static int sh_dmac_get_dma_residue(struct dma_channel *chan)
{
if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE))
if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
return 0;

return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
return ctrl_inl(dma_base_addr[chan->chan] + TCR)
<< calc_xmit_shift(chan);
}

#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
#define dmaor_read_reg() ctrl_inw(DMAOR)
#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
#else
#define dmaor_read_reg() ctrl_inl(DMAOR)
#define dmaor_write_reg(data) ctrl_outl(data, DMAOR)
#endif

static inline int dmaor_reset(void)
static inline int dmaor_reset(int no)
{
unsigned long dmaor = dmaor_read_reg();
unsigned long dmaor = dmaor_read_reg(no);

/* Try to clear the error flags first, incase they are set */
dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
dmaor_write_reg(dmaor);
dmaor_write_reg(no, dmaor);

dmaor |= DMAOR_INIT;
dmaor_write_reg(dmaor);
dmaor_write_reg(no, dmaor);

/* See if we got an error again */
if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
if ((dmaor_read_reg(no) & (DMAOR_AE | DMAOR_NMIF))) {
printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
return -EINVAL;
}
Expand All @@ -237,10 +235,33 @@ static inline int dmaor_reset(void)
#if defined(CONFIG_CPU_SH4)
static irqreturn_t dma_err(int irq, void *dummy)
{
dmaor_reset();
#if defined(DMAC_IRQ_MULTI)
int cnt = 0;
switch (irq) {
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
case DMTE6_IRQ:
cnt++;
#endif
case DMTE0_IRQ:
if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
disable_irq(irq);
/* DMA multi and error IRQ */
return IRQ_HANDLED;
}
default:
return IRQ_NONE;
}
#else
dmaor_reset(0);
#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
dmaor_reset(1);
#endif
disable_irq(irq);

return IRQ_HANDLED;
#endif
}
#endif

Expand All @@ -259,33 +280,70 @@ static struct dma_info sh_dmac_info = {
.flags = DMAC_CHANNELS_TEI_CAPABLE,
};

static unsigned int get_dma_error_irq(int n)
{
#if defined(DMAC_IRQ_MULTI)
return (n == 0) ? get_dmte_irq(0) : get_dmte_irq(6);
#else
return (n == 0) ? DMAE0_IRQ :
#if defined(DMAE1_IRQ)
DMAE1_IRQ;
#else
-1;
#endif
#endif
}

static int __init sh_dmac_init(void)
{
struct dma_info *info = &sh_dmac_info;
int i;

#ifdef CONFIG_CPU_SH4
i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
if (unlikely(i < 0))
return i;
int n;

for (n = 0; n < NR_DMAE; n++) {
i = request_irq(get_dma_error_irq(n), dma_err,
#if defined(DMAC_IRQ_MULTI)
IRQF_SHARED,
#else
IRQF_DISABLED,
#endif
dmae_name[n], (void *)dmae_name[n]);
if (unlikely(i < 0)) {
printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
return i;
}
}
#endif /* CONFIG_CPU_SH4 */

/*
* Initialize DMAOR, and clean up any error flags that may have
* been set.
*/
i = dmaor_reset();
i = dmaor_reset(0);
if (unlikely(i != 0))
return i;
#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
defined(CONFIG_CPU_SUBTYPE_SH7785)
i = dmaor_reset(1);
if (unlikely(i != 0))
return i;
#endif

return register_dmac(info);
}

static void __exit sh_dmac_exit(void)
{
#ifdef CONFIG_CPU_SH4
free_irq(DMAE_IRQ, 0);
#endif
int n;

for (n = 0; n < NR_DMAE; n++) {
free_irq(get_dma_error_irq(n), (void *)dmae_name[n]);
}
#endif /* CONFIG_CPU_SH4 */
unregister_dmac(&sh_dmac_info);
}

Expand Down
75 changes: 0 additions & 75 deletions arch/sh/drivers/dma/dma-sh.h
View file

This file was deleted.

Loading

0 comments on commit 71b973a

Please sign in to comment.