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yaml
---
r: 183188
b: refs/heads/master
c: 9a219a9
h: refs/heads/master
v: v3
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Sekhar Nori authored and Kevin Hilman committed Feb 4, 2010
1 parent c659566 commit 723722f
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Showing 3 changed files with 19 additions and 13 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: d2de05827cce9438dfc61d5a4cf13b6ca82ebdee
refs/heads/master: 9a219a9ecf49ab156df4c18267ade4d468d9930e
15 changes: 3 additions & 12 deletions trunk/arch/arm/mach-davinci/clock.c
Original file line number Diff line number Diff line change
Expand Up @@ -376,7 +376,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
locktime = ((2000 * prediv) / 100);
prediv = (prediv - 1) | PLLDIV_EN;
} else {
locktime = 20;
locktime = PLL_LOCK_TIME;
}
if (postdiv)
postdiv = (postdiv - 1) | PLLDIV_EN;
Expand All @@ -389,12 +389,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
__raw_writel(ctrl, pll->base + PLLCTL);

/*
* Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
* to bypass mode. Delay of 1us ensures we are good for all > 4MHz
* OSCIN/CLKIN inputs. Typically the input is ~25MHz.
*/
udelay(1);
udelay(PLL_BYPASS_TIME);

/* Reset and enable PLL */
ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
Expand All @@ -408,11 +403,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
if (pll->flags & PLL_HAS_POSTDIV)
__raw_writel(postdiv, pll->base + POSTDIV);

/*
* Wait for PLL to reset properly, OMAP-L138 datasheet says
* 'min' time = 125ns
*/
udelay(1);
udelay(PLL_RESET_TIME);

/* Bring PLL out of reset */
ctrl |= PLLCTL_PLLRST;
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15 changes: 15 additions & 0 deletions trunk/arch/arm/mach-davinci/clock.h
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,21 @@
#define PLLDIV_EN BIT(15)
#define PLLDIV_RATIO_MASK 0x1f

/*
* OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
* cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
* ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
* is ~25MHz. Units are micro seconds.
*/
#define PLL_BYPASS_TIME 1
/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
#define PLL_RESET_TIME 1
/*
* From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
* Units are micro seconds.
*/
#define PLL_LOCK_TIME 20

struct pll_data {
u32 phys_base;
void __iomem *base;
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