---

yaml --- r: 304099 b: refs/heads/master c: af46810 h: refs/heads/master i: 304097: 18e8972 304095: e111b60 v: v3
git-mirror · May 10, 2012 · 72ac2aa · 72ac2aa
1 parent fb05630
commit 72ac2aa
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diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c542fb79fba4c63aa6e2a27f90373b0516614eca
+refs/heads/master: af4681097b23fe9c63a03d774de7c742fa3a920e
diff --git a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt
@@ -0,0 +1,18 @@
+NVIDIA Tegra30 MC(Memory Controller)
+
+Required properties:
+- compatible : "nvidia,tegra30-mc"
+- reg : Should contain 4 register ranges(address and length); see the
+  example below. Note that the MC registers are interleaved with the
+  SMMU registers, and hence must be represented as multiple ranges.
+- interrupts : Should contain MC General interrupt.
+
+Example:
+	mc {
+		compatible = "nvidia,tegra30-mc";
+		reg = <0x7000f000 0x010
+		       0x7000f03c 0x1b4
+		       0x7000f200 0x028
+		       0x7000f284 0x17c>;
+		interrupts = <0 77 0x04>;
+	};
diff --git a/trunk/arch/arm/mach-tegra/Kconfig b/trunk/arch/arm/mach-tegra/Kconfig
@@ -43,6 +43,8 @@ config ARCH_TEGRA_3x_SOC
 	select ARM_ERRATA_764369
 	select PL310_ERRATA_769419 if CACHE_L2X0
 	select CPU_FREQ_TABLE if CPU_FREQ
+	select MEMORY
+	select TEGRA30_MC
 	help
 	  Support for NVIDIA Tegra T30 processor family, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

diff --git a/trunk/drivers/memory/Kconfig b/trunk/drivers/memory/Kconfig
@@ -24,4 +24,8 @@ config TEGRA20_MC
 	bool
 	depends on ARCH_TEGRA_2x_SOC
 
+config TEGRA30_MC
+	bool
+	depends on ARCH_TEGRA_3x_SOC
+
 endif
diff --git a/trunk/drivers/memory/Makefile b/trunk/drivers/memory/Makefile
@@ -4,3 +4,4 @@
 
 obj-$(CONFIG_TI_EMIF)		+= emif.o
 obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
+obj-$(CONFIG_TEGRA30_MC)	+= tegra30-mc.o
Original file line number	Diff line number	Diff line change
Expand Up		@@ -4,3 +4,4 @@

		obj-$(CONFIG_TI_EMIF) += emif.o
		obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
		obj-$(CONFIG_TEGRA30_MC) += tegra30-mc.o