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yaml --- r: 170413 b: refs/heads/master c: df8b4ec h: refs/heads/master i: 170411: 1349d1d v: v3
git-mirror · Oct 5, 2009 · 733c2b0 · 733c2b0
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diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
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-refs/heads/master: ee1262dbc65ce0b6234a915d8432171e8d77f518
+refs/heads/master: df8b4ec8b15a5db84706548149add3131c3af8ba
diff --git a/trunk/.gitignore b/trunk/.gitignore
@@ -25,7 +25,6 @@
 *.elf
 *.bin
 *.gz
-*.bz2
 *.lzma
 *.patch
 *.gcno

diff --git a/...ion/ABI/testing/sysfs-class-uwb_rc-wusbhc → ...entation/ABI/testing/sysfs-class-usb_host b/...ion/ABI/testing/sysfs-class-uwb_rc-wusbhc → ...entation/ABI/testing/sysfs-class-usb_host
@@ -1,4 +1,4 @@
-What:           /sys/class/uwb_rc/uwbN/wusbhc/wusb_chid
+What:           /sys/class/usb_host/usb_hostN/wusb_chid
 Date:           July 2008
 KernelVersion:  2.6.27
 Contact:        David Vrabel <david.vrabel@csr.com>
@@ -9,7 +9,7 @@ Description:
 
                 Set an all zero CHID to stop the host controller.
 
-What:           /sys/class/uwb_rc/uwbN/wusbhc/wusb_trust_timeout
+What:           /sys/class/usb_host/usb_hostN/wusb_trust_timeout
 Date:           July 2008
 KernelVersion:  2.6.27
 Contact:        David Vrabel <david.vrabel@csr.com>

diff --git a/trunk/Documentation/ABI/testing/sysfs-devices-cache_disable b/trunk/Documentation/ABI/testing/sysfs-devices-cache_disable
@@ -0,0 +1,18 @@
+What:      /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
+Date:      August 2008
+KernelVersion:	2.6.27
+Contact:	mark.langsdorf@amd.com
+Description:	These files exist in every cpu's cache index directories.
+		There are currently 2 cache_disable_# files in each
+		directory.  Reading from these files on a supported
+		processor will return that cache disable index value
+		for that processor and node.  Writing to one of these
+		files will cause the specificed cache index to be disabled.
+
+		Currently, only AMD Family 10h Processors support cache index
+		disable, and only for their L3 caches.  See the BIOS and
+		Kernel Developer's Guide at
+		http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
+		for formatting information and other details on the
+		cache index disable.
+Users:    joachim.deguara@amd.com
diff --git a/trunk/Documentation/ABI/testing/sysfs-devices-system-cpu b/trunk/Documentation/ABI/testing/sysfs-devices-system-cpu
diff --git a/trunk/Documentation/DocBook/tracepoint.tmpl b/trunk/Documentation/DocBook/tracepoint.tmpl
@@ -86,9 +86,4 @@
 !Iinclude/trace/events/irq.h
   </chapter>
 
-  <chapter id="signal">
-   <title>SIGNAL</title>
-!Iinclude/trace/events/signal.h
-  </chapter>
-
 </book>
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