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sh: pci: Rewrite SH7751 PCI support to follow SH7780.
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This follows the similar sort of scheme that the refactored SH7780 code
uses, using a 64MB CS3 mapping to handle the window0 case, and simply
discarding window1. This vastly simplifies the code, and allows most of
the board-specific setup to go die.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt committed Apr 20, 2009
1 parent a5b0804 commit 757e3c1
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Showing 10 changed files with 76 additions and 305 deletions.
3 changes: 2 additions & 1 deletion arch/sh/drivers/pci/Kconfig
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Expand Up @@ -23,7 +23,8 @@ config PCI_NEW
bool
depends on PCI
default y if CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7780 || \
CPU_SUBTYPE_SH7785 || CPU_SH5
CPU_SUBTYPE_SH7785 || CPU_SH5 || \
CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R

# This is also board-specific
config PCI_AUTO
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2 changes: 1 addition & 1 deletion arch/sh/drivers/pci/Makefile
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Expand Up @@ -16,7 +16,7 @@ obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
pci-dreamcast.o
obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o
obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o
obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o
obj-$(CONFIG_SH_SH03) += fixups-sh03.o
obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o
obj-$(CONFIG_SH_SH7785LCR) += fixups-r7780rp.o
obj-$(CONFIG_SH_SDK7780) += fixups-sdk7780.o
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31 changes: 0 additions & 31 deletions arch/sh/drivers/pci/ops-landisk.c
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Expand Up @@ -15,37 +15,6 @@
#include <linux/pci.h>
#include "pci-sh4.h"

static struct resource sh7751_io_resource = {
.name = "SH7751 IO",
.start = SH7751_PCI_IO_BASE,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};

static struct resource sh7751_mem_resource = {
.name = "SH7751 mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};

struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0x3ff},
{NULL, NULL, NULL, 0, 0},
};

static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS3_BASE_ADDR,
.size = (64 << 20), /* 64MB */
},
};

int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}

int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
/*
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33 changes: 0 additions & 33 deletions arch/sh/drivers/pci/ops-lboxre2.c
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Expand Up @@ -21,36 +21,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
return lboxre2_irq_tab[slot];
}

static struct resource sh7751_io_resource = {
.name = "SH7751_IO",
.start = SH7751_PCI_IO_BASE ,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};

static struct resource sh7751_mem_resource = {
.name = "SH7751_mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};

extern struct pci_ops sh7751_pci_ops;

struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ NULL, NULL, NULL, 0, 0 },
};

static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS3_BASE_ADDR,
.size = 0x04000000,
},
};

int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}
34 changes: 0 additions & 34 deletions arch/sh/drivers/pci/ops-rts7751r2d.c
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Expand Up @@ -29,37 +29,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
return rts7751r2d_irq_tab[slot];
}

static struct resource sh7751_io_resource = {
.name = "SH7751_IO",
.start = 0x4000,
.end = SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};

static struct resource sh7751_mem_resource = {
.name = "SH7751_mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};

extern struct pci_ops sh7751_pci_ops;

struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ NULL, NULL, NULL, 0, 0 },
};

static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS3_BASE_ADDR,
.size = 0x04000000,
},
};

int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}

45 changes: 0 additions & 45 deletions arch/sh/drivers/pci/ops-sh03.c
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This file was deleted.

49 changes: 0 additions & 49 deletions arch/sh/drivers/pci/ops-snapgear.c
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Expand Up @@ -18,55 +18,6 @@
#include <linux/pci.h>
#include "pci-sh4.h"

#define SNAPGEAR_PCI_IO 0x4000
#define SNAPGEAR_PCI_MEM 0xfd000000

/* PCI: default LOCAL memory window sizes (seen from PCI bus) */
#define SNAPGEAR_LSR0_SIZE (64*(1<<20)) //64MB
#define SNAPGEAR_LSR1_SIZE (64*(1<<20)) //64MB

static struct resource sh7751_io_resource = {
.name = "SH7751 IO",
.start = SNAPGEAR_PCI_IO,
.end = SNAPGEAR_PCI_IO + (64*1024) - 1, /* 64KiB I/O */
.flags = IORESOURCE_IO,
};

static struct resource sh7751_mem_resource = {
.name = "SH7751 mem",
.start = SNAPGEAR_PCI_MEM,
.end = SNAPGEAR_PCI_MEM + (64*1024*1024) - 1, /* 64MiB mem */
.flags = IORESOURCE_MEM,
};

struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ 0, }
};

static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SNAPGEAR_LSR0_SIZE,
},

.window1 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SNAPGEAR_LSR1_SIZE,
},
};

/*
* Initialize the SnapGear PCI interface
* Setup hardware to be Central Funtion
* Copy the BSR regs to the PCI interface
* Setup PCI windows into local RAM
*/
int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}

int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
{
int irq = -1;
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36 changes: 0 additions & 36 deletions arch/sh/drivers/pci/ops-titan.c
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Expand Up @@ -36,39 +36,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)

return irq;
}

static struct resource sh7751_io_resource = {
.name = "SH7751_IO",
.start = SH7751_PCI_IO_BASE,
.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};

static struct resource sh7751_mem_resource = {
.name = "SH7751_mem",
.start = SH7751_PCI_MEMORY_BASE,
.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM
};

struct pci_channel board_pci_channels[] = {
{ sh7751_pci_init, &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ NULL, NULL, NULL, 0, 0 },
};

static struct sh4_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SH7751_MEM_REGION_SIZE*2, /* cs2 and cs3 */
},

.window1 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SH7751_MEM_REGION_SIZE*2,
},
};

int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&board_pci_channels[0], &sh7751_pci_map);
}
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