---

yaml
---
r: 63824
b: refs/heads/master
c: b247bbf
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6a0ed91e361a93ee1efb4c20c4967024ed2a8dd7
+refs/heads/master: b247bbf1da69ce376aa1ceb8057331214589e366

trunk/Documentation/lguest/Makefile

@@ -13,9 +13,7 @@ LGUEST_GUEST_TOP := ($(CONFIG_PAGE_OFFSET) - 0x08000000)
 
 CFLAGS:=-Wall -Wmissing-declarations -Wmissing-prototypes -O3 -Wl,-T,lguest.lds
 LDLIBS:=-lz
-# Removing this works for some versions of ld.so (eg. Ubuntu Feisty) and
-# not others (eg. FC7).
-LDFLAGS+=-static
+
 all: lguest.lds lguest
 
 # The linker script on x86 is so complex the only way of creating one

trunk/Documentation/sched-design-CFS.txt

@@ -83,7 +83,7 @@ Some implementation details:
    CFS uses nanosecond granularity accounting and does not rely on any
    jiffies or other HZ detail. Thus the CFS scheduler has no notion of
    'timeslices' and has no heuristics whatsoever. There is only one
-   central tunable (you have to switch on CONFIG_SCHED_DEBUG):
+   central tunable:
 
          /proc/sys/kernel/sched_granularity_ns
 

trunk/arch/sparc/kernel/prom.c

@@ -102,21 +102,6 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
 }
 EXPORT_SYMBOL(of_set_property);
 
-int of_find_in_proplist(const char *list, const char *match, int len)
-{
-	while (len > 0) {
-		int l;
-
-		if (!strcmp(list, match))
-			return 1;
-		l = strlen(list) + 1;
-		list += l;
-		len -= l;
-	}
-	return 0;
-}
-EXPORT_SYMBOL(of_find_in_proplist);
-
 static unsigned int prom_early_allocated;
 
 static void * __init prom_early_alloc(unsigned long size)

trunk/arch/sparc64/kernel/cpu.c

@@ -1,7 +1,7 @@
 /* cpu.c: Dinky routines to look for the kind of Sparc cpu
  *        we are on.
  *
- * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  */
 
 #include <linux/kernel.h>
@@ -13,7 +13,6 @@
 #include <asm/fpumacro.h>
 #include <asm/cpudata.h>
 #include <asm/spitfire.h>
-#include <asm/oplib.h>
 
 DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
 
@@ -62,40 +61,21 @@ struct cpu_iu_info linux_sparc_chips[] = {
 
 #define NSPARCCHIPS  ARRAY_SIZE(linux_sparc_chips)
 
-char *sparc_cpu_type;
-char *sparc_fpu_type;
+char *sparc_cpu_type = "cpu-oops";
+char *sparc_fpu_type = "fpu-oops";
 
 unsigned int fsr_storage;
 
-static void __init sun4v_cpu_probe(void)
-{
-	switch (sun4v_chip_type) {
-	case SUN4V_CHIP_NIAGARA1:
-		sparc_cpu_type = "UltraSparc T1 (Niagara)";
-		sparc_fpu_type = "UltraSparc T1 integrated FPU";
-		break;
-
-	case SUN4V_CHIP_NIAGARA2:
-		sparc_cpu_type = "UltraSparc T2 (Niagara2)";
-		sparc_fpu_type = "UltraSparc T2 integrated FPU";
-		break;
-
-	default:
-		printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
-		       prom_cpu_compatible);
-		sparc_cpu_type = "Unknown SUN4V CPU";
-		sparc_fpu_type = "Unknown SUN4V FPU";
-		break;
-	}
-}
-
 void __init cpu_probe(void)
 {
 	unsigned long ver, fpu_vers, manuf, impl, fprs;
 	int i;
 
-	if (tlb_type == hypervisor)
-		return sun4v_cpu_probe();
+	if (tlb_type == hypervisor) {
+		sparc_cpu_type = "UltraSparc T1 (Niagara)";
+		sparc_fpu_type = "UltraSparc T1 integrated FPU";
+		return;
+	}
 
 	fprs = fprs_read();
 	fprs_write(FPRS_FEF);

trunk/arch/sparc64/kernel/head.S

@@ -97,8 +97,7 @@ sparc64_boot:
 	.globl	prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
 	.globl	prom_boot_mapped_pc, prom_boot_mapping_mode
 	.globl	prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
-	.globl	prom_compatible_name, prom_cpu_path, prom_cpu_compatible
-	.globl	is_sun4v, sun4v_chip_type
+	.globl	is_sun4v
 prom_peer_name:
 	.asciz	"peer"
 prom_compatible_name:
@@ -107,8 +106,6 @@ prom_finddev_name:
 	.asciz	"finddevice"
 prom_chosen_path:
 	.asciz	"/chosen"
-prom_cpu_path:
-	.asciz	"/cpu"
 prom_getprop_name:
 	.asciz	"getprop"
 prom_mmu_name:
@@ -123,13 +120,9 @@ prom_unmap_name:
 	.asciz	"unmap"
 prom_sun4v_name:
 	.asciz	"sun4v"
-prom_niagara_prefix:
-	.asciz	"SUNW,UltraSPARC-T"
 	.align	4
 prom_root_compatible:
 	.skip	64
-prom_cpu_compatible:
-	.skip	64
 prom_root_node:
 	.word	0
 prom_mmu_ihandle_cache:
@@ -145,8 +138,6 @@ prom_boot_mapping_phys_low:
 	.xword	0
 is_sun4v:
 	.word	0
-sun4v_chip_type:
-	.word	SUN4V_CHIP_INVALID
 1:
 	rd	%pc, %l0
 
@@ -305,94 +296,21 @@ sun4v_chip_type:
 	sethi	%hi(prom_sun4v_name), %g7
 	or	%g7, %lo(prom_sun4v_name), %g7
 	mov	5, %g3
-90:	ldub	[%g7], %g2
+1:	ldub	[%g7], %g2
 	ldub	[%g1], %g4
 	cmp	%g2, %g4
-	bne,pn	%icc, 80f
+	bne,pn	%icc, 2f
 	 add	%g7, 1, %g7
 	subcc	%g3, 1, %g3
-	bne,pt	%xcc, 90b
+	bne,pt	%xcc, 1b
 	 add	%g1, 1, %g1
 
 	sethi	%hi(is_sun4v), %g1
 	or	%g1, %lo(is_sun4v), %g1
 	mov	1, %g7
 	stw	%g7, [%g1]
 
-	/* cpu_node = prom_finddevice("/cpu") */
-	mov	(1b - prom_finddev_name), %l1
-	mov	(1b - prom_cpu_path), %l2
-	sub	%l0, %l1, %l1
-	sub	%l0, %l2, %l2
-	sub	%sp, (192 + 128), %sp
-
-	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "finddevice"
-	mov	1, %l3
-	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 1
-	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
-	stx	%l2, [%sp + 2047 + 128 + 0x18]	! arg1, "/cpu"
-	stx	%g0, [%sp + 2047 + 128 + 0x20]	! ret1
-	call	%l7
-	 add	%sp, (2047 + 128), %o0		! argument array
-
-	ldx	[%sp + 2047 + 128 + 0x20], %l4	! cpu device node
-
-	mov	(1b - prom_getprop_name), %l1
-	mov	(1b - prom_compatible_name), %l2
-	mov	(1b - prom_cpu_compatible), %l5
-	sub	%l0, %l1, %l1
-	sub	%l0, %l2, %l2
-	sub	%l0, %l5, %l5
-
-	/* prom_getproperty(cpu_node, "compatible",
-	 *                  &prom_cpu_compatible, 64)
-	 */
-	stx	%l1, [%sp + 2047 + 128 + 0x00]	! service, "getprop"
-	mov	4, %l3
-	stx	%l3, [%sp + 2047 + 128 + 0x08]	! num_args, 4
-	mov	1, %l3
-	stx	%l3, [%sp + 2047 + 128 + 0x10]	! num_rets, 1
-	stx	%l4, [%sp + 2047 + 128 + 0x18]	! arg1, cpu_node
-	stx	%l2, [%sp + 2047 + 128 + 0x20]	! arg2, "compatible"
-	stx	%l5, [%sp + 2047 + 128 + 0x28]	! arg3, &prom_cpu_compatible
-	mov	64, %l3
-	stx	%l3, [%sp + 2047 + 128 + 0x30]	! arg4, size
-	stx	%g0, [%sp + 2047 + 128 + 0x38]	! ret1
-	call	%l7
-	 add	%sp, (2047 + 128), %o0		! argument array
-
-	add	%sp, (192 + 128), %sp
-
-	sethi	%hi(prom_cpu_compatible), %g1
-	or	%g1, %lo(prom_cpu_compatible), %g1
-	sethi	%hi(prom_niagara_prefix), %g7
-	or	%g7, %lo(prom_niagara_prefix), %g7
-	mov	17, %g3
-90:	ldub	[%g7], %g2
-	ldub	[%g1], %g4
-	cmp	%g2, %g4
-	bne,pn	%icc, 4f
-	 add	%g7, 1, %g7
-	subcc	%g3, 1, %g3
-	bne,pt	%xcc, 90b
-	 add	%g1, 1, %g1
-
-	sethi	%hi(prom_cpu_compatible), %g1
-	or	%g1, %lo(prom_cpu_compatible), %g1
-	ldub	[%g1 + 17], %g2
-	cmp	%g2, '1'
-	be,pt	%xcc, 5f
-	 mov	SUN4V_CHIP_NIAGARA1, %g4
-	cmp	%g2, '2'
-	be,pt	%xcc, 5f
-	 mov	SUN4V_CHIP_NIAGARA2, %g4
-4:
-	mov	SUN4V_CHIP_UNKNOWN, %g4
-5:	sethi	%hi(sun4v_chip_type), %g2
-	or	%g2, %lo(sun4v_chip_type), %g2
-	stw	%g4, [%g2]
-
-80:
+2:
 	BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
 	BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
 	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
@@ -496,32 +414,13 @@ niagara_tlb_fixup:
 	stw	%g2, [%g1 + %lo(tlb_type)]
 
 	/* Patch copy/clear ops.  */
-	sethi	%hi(sun4v_chip_type), %g1
-	lduw	[%g1 + %lo(sun4v_chip_type)], %g1
-	cmp	%g1, SUN4V_CHIP_NIAGARA1
-	be,pt	%xcc, niagara_patch
-	 cmp	%g1, SUN4V_CHIP_NIAGARA2
-	be,pt	%xcc, niagara_patch
-	 nop
-
-	call	generic_patch_copyops
-	 nop
-	call	generic_patch_bzero
-	 nop
-	call	generic_patch_pageops
-	 nop
-
-	ba,a,pt	%xcc, 80f
-
-niagara_patch:
 	call	niagara_patch_copyops
 	 nop
 	call	niagara_patch_bzero
 	 nop
 	call	niagara_patch_pageops
 	 nop
 
-80:
 	/* Patch TLB/cache ops.  */
 	call	hypervisor_patch_cachetlbops
 	 nop