---

yaml
---
r: 25524
b: refs/heads/master
c: c14038c
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: dbc8700e27a94621de9d22c506c67913e0121501
+refs/heads/master: c14038c39ddd9c14225907a05a6ac4d91d645ef1

trunk/Documentation/memory-barriers.txt

@@ -610,6 +610,7 @@ loads.  Consider the following sequence of events:
 
 	CPU 1			CPU 2
 	=======================	=======================
+		{ B = 7; X = 9; Y = 8; C = &Y }
 	STORE A = 1
 	STORE B = 2
 	<write barrier>
@@ -651,7 +652,20 @@ In the above example, CPU 2 perceives that B is 7, despite the load of *C
 (which would be B) coming after the the LOAD of C.
 
 If, however, a data dependency barrier were to be placed between the load of C
-and the load of *C (ie: B) on CPU 2, then the following will occur:
+and the load of *C (ie: B) on CPU 2:
+
+	CPU 1			CPU 2
+	=======================	=======================
+		{ B = 7; X = 9; Y = 8; C = &Y }
+	STORE A = 1
+	STORE B = 2
+	<write barrier>
+	STORE C = &B		LOAD X
+	STORE D = 4		LOAD C (gets &B)
+				<data dependency barrier>
+				LOAD *C (reads B)
+
+then the following will occur:
 
 	+-------+       :      :                :       :
 	|       |       +------+                +-------+