Blackfin arch: remove support for Anomaly 05000125 as it doesnt exist…

… on any supported processor/silicon Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
git-mirror · Aug 6, 2008 · 778307d · 778307d
1 parent d6a2989
commit 778307d
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Showing 7 changed files with 2 additions and 178 deletions.
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S
@@ -105,36 +105,17 @@ ENTRY(__start)
 	R1 = [p0];
 	R0 = ~ENICPLB;
 	R0 = R0 & R1;
-
-	/* Anomaly 05000125 */
-#if ANOMALY_05000125
-	CLI R2;
-	SSYNC;
-#endif
 	[p0] = R0;
 	SSYNC;
-#if ANOMALY_05000125
-	STI R2;
-#endif
 
 	/* Turn off the dcache */
 	p0.l = LO(DMEM_CONTROL);
 	p0.h = HI(DMEM_CONTROL);
 	R1 = [p0];
 	R0 = ~ENDCPLB;
 	R0 = R0 & R1;
-
-	/* Anomaly 05000125 */
-#if ANOMALY_05000125
-	CLI R2;
-	SSYNC;
-#endif
 	[p0] = R0;
 	SSYNC;
-#if ANOMALY_05000125
-	STI R2;
-#endif
-
 
 #if defined(CONFIG_BF527)
 	p0.h = hi(EMAC_SYSTAT);

diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
@@ -116,35 +116,17 @@ ENTRY(__start)
 	R1 = [p0];
 	R0 = ~ENICPLB;
 	R0 = R0 & R1;
-
-	/* Anomaly 05000125 */
-#if ANOMALY_05000125
-	CLI R2;
-	SSYNC;
-#endif
 	[p0] = R0;
 	SSYNC;
-#if ANOMALY_05000125
-	STI R2;
-#endif
 
 	/* Turn off the dcache */
 	p0.l = LO(DMEM_CONTROL);
 	p0.h = HI(DMEM_CONTROL);
 	R1 = [p0];
 	R0 = ~ENDCPLB;
 	R0 = R0 & R1;
-
-	/* Anomaly 05000125 */
-#if ANOMALY_05000125
-	CLI R2;
-	SSYNC;
-#endif
 	[p0] = R0;
 	SSYNC;
-#if ANOMALY_05000125
-	STI R2;
-#endif
 
 	/* Initialise UART - when booting from u-boot, the UART is not disabled
 	 * so if we dont initalize here, our serial console gets hosed */

diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
@@ -105,66 +105,29 @@ ENTRY(__start)
 	R1 = [p0];
 	R0 = ~ENICPLB;
 	R0 = R0 & R1;
-
-	/* Anomaly 05000125 */
-#if ANOMALY_05000125
-	CLI R2;
-	SSYNC;
-#endif
 	[p0] = R0;
 	SSYNC;
-#if ANOMALY_05000125
-	STI R2;
-#endif
 
 	/* Turn off the dcache */
 	p0.l = LO(DMEM_CONTROL);
 	p0.h = HI(DMEM_CONTROL);
 	R1 = [p0];
 	R0 = ~ENDCPLB;
 	R0 = R0 & R1;
-
-	/* Anomaly 05000125 */
-#if ANOMALY_05000125
-	CLI R2;
-	SSYNC;
-#endif
 	[p0] = R0;
 	SSYNC;
-#if ANOMALY_05000125
-	STI R2;
-#endif
 
 	/* Initialise General-Purpose I/O Modules on BF537 */
-	/* Rev 0.0 Anomaly 05000212 - PORTx_FER,
-	 * PORT_MUX Registers Do Not accept "writes" correctly:
-	 */
 	p0.h = hi(BFIN_PORT_MUX);
 	p0.l = lo(BFIN_PORT_MUX);
-#if ANOMALY_05000212
-	R0.L = W[P0]; /* Read */
-	SSYNC;
-#endif
 	R0 = (PGDE_UART | PFTE_UART)(Z);
-#if ANOMALY_05000212
-	W[P0] = R0.L; /* Write */
-	SSYNC;
-#endif
 	W[P0] = R0.L; /* Enable both UARTS */
 	SSYNC;
 
+	/* Enable peripheral function of PORTF for UART0 and UART1 */
 	p0.h = hi(PORTF_FER);
 	p0.l = lo(PORTF_FER);
-#if ANOMALY_05000212
-	R0.L = W[P0]; /* Read */
-	SSYNC;
-#endif
 	R0 = 0x000F(Z);
-#if ANOMALY_05000212
-	W[P0] = R0.L; /* Write */
-	SSYNC;
-#endif
-	/* Enable peripheral function of PORTF for UART0 and UART1 */
 	W[P0] = R0.L;
 	SSYNC;
 

diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
@@ -105,34 +105,17 @@ ENTRY(__start)
 	R1 = [p0];
 	R0 = ~ENICPLB;
 	R0 = R0 & R1;
-
-#if ANOMALY_05000125
-	CLI R2;
-	SSYNC;
-#endif
 	[p0] = R0;
 	SSYNC;
-#if ANOMALY_05000125
-	STI R2;
-#endif
 
 	/* Turn off the dcache */
 	p0.l = LO(DMEM_CONTROL);
 	p0.h = HI(DMEM_CONTROL);
 	R1 = [p0];
 	R0 = ~ENDCPLB;
 	R0 = R0 & R1;
-
-	/* Anomaly 05000125 */
-#if ANOMALY_05000125
-	CLI R2;
-	SSYNC;
-#endif
 	[p0] = R0;
 	SSYNC;
-#if ANOMALY_05000125
-	STI R2;
-#endif
 
 	/* Initialise UART - when booting from u-boot, the UART is not disabled
 	 * so if we dont initalize here, our serial console gets hosed */

diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
@@ -3,7 +3,7 @@
 #
 
 obj-y := \
-	cache.o cacheinit.o entry.o \
+	cache.o entry.o \
 	interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
 
 obj-$(CONFIG_PM)          += pm.o dpmc_modes.o

diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -39,11 +39,7 @@
 #define bfin_read_SRAM_BASE_ADDRESS()        bfin_read32(SRAM_BASE_ADDRESS)
 #define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
 #define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
-#if ANOMALY_05000125
-extern void bfin_write_DMEM_CONTROL(unsigned int val);
-#else
 #define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
-#endif
 #define bfin_read_DCPLB_STATUS()             bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)         bfin_write32(DCPLB_STATUS,val)
 #define bfin_read_DCPLB_FAULT_ADDR()         bfin_read32(DCPLB_FAULT_ADDR)
@@ -129,11 +125,7 @@ extern void bfin_write_DMEM_CONTROL(unsigned int val);
 #define DTEST_DATA3            0xFFE0040C
 */
 #define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
-#if ANOMALY_05000125
-extern void bfin_write_IMEM_CONTROL(unsigned int val);
-#else
 #define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
-#endif
 #define bfin_read_ICPLB_STATUS()             bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)         bfin_write32(ICPLB_STATUS,val)
 #define bfin_read_ICPLB_FAULT_ADDR()         bfin_read32(ICPLB_FAULT_ADDR)