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Merge branch 'next/devel-samsung' of git://git.kernel.org/pub/scm/lin…
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…ux/kernel/git/kgene/linux-samsung into next/soc

From Kukjin Kim <kgene.kim@samsung.com>:

This is general development for Samsung stuff for v3.6

* 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API
  ARM: EXYNOS: Add missing static storage class specifier in pmu.c file
  ARM: EXYNOS: Make combiner_init function static
  ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12
  ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann committed Jul 17, 2012
2 parents ff60914 + 2aa1ecf commit 77e77e1
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Showing 8 changed files with 92 additions and 26 deletions.
3 changes: 2 additions & 1 deletion arch/arm/mach-exynos/common.c
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Expand Up @@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
.map = combiner_irq_domain_map,
};

void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
static void __init combiner_init(void __iomem *combiner_base,
struct device_node *np)
{
int i, irq, irq_base;
unsigned int max_nr, nr_irq;
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5 changes: 5 additions & 0 deletions arch/arm/mach-exynos/include/mach/regs-pmu.h
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Expand Up @@ -232,6 +232,11 @@

#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)

#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)

#define EXYNOS5_SYS_WDTRESET (1 << 20)

#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
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20 changes: 15 additions & 5 deletions arch/arm/mach-exynos/include/mach/regs-usb-phy.h
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Expand Up @@ -35,11 +35,21 @@
#define PHY1_COMMON_ON_N (1 << 7)
#define PHY0_COMMON_ON_N (1 << 4)
#define PHY0_ID_PULLUP (1 << 2)
#define CLKSEL_MASK (0x3 << 0)
#define CLKSEL_SHIFT (0)
#define CLKSEL_48M (0x0 << 0)
#define CLKSEL_12M (0x2 << 0)
#define CLKSEL_24M (0x3 << 0)

#define EXYNOS4_CLKSEL_SHIFT (0)

#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
#define EXYNOS4210_CLKSEL_24M (0x3 << 0)

#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)

#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
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18 changes: 16 additions & 2 deletions arch/arm/mach-exynos/pmu.c
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Expand Up @@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
};

void __iomem *exynos5_list_both_cnt_feed[] = {
static void __iomem *exynos5_list_both_cnt_feed[] = {
EXYNOS5_ARM_CORE0_OPTION,
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_ARM_COMMON_OPTION,
Expand All @@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = {
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
};

void __iomem *exynos5_list_diable_wfi_wfe[] = {
static void __iomem *exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_FSYS_ARM_OPTION,
EXYNOS5_ISP_ARM_OPTION,
Expand Down Expand Up @@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)

static int __init exynos_pmu_init(void)
{
unsigned int value;

exynos_pmu_config = exynos4210_pmu_config;

if (soc_is_exynos4210()) {
Expand All @@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void)
exynos_pmu_config = exynos4x12_pmu_config;
pr_info("EXYNOS4x12 PMU Initialize\n");
} else if (soc_is_exynos5250()) {
/*
* When SYS_WDTRESET is set, watchdog timer reset request
* is ignored by power management unit.
*/
value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);

value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);

exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
} else {
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60 changes: 44 additions & 16 deletions arch/arm/mach-exynos/setup-usb-phy.c
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Expand Up @@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
struct clk *xusbxti_clk;
u32 phyclk;

/* set clock frequency for PLL */
phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;

xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
switch (clk_get_rate(xusbxti_clk)) {
case 12 * MHZ:
phyclk |= CLKSEL_12M;
break;
case 24 * MHZ:
phyclk |= CLKSEL_24M;
break;
default:
case 48 * MHZ:
/* default reference clock */
break;
if (soc_is_exynos4210()) {
/* set clock frequency for PLL */
phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;

switch (clk_get_rate(xusbxti_clk)) {
case 12 * MHZ:
phyclk |= EXYNOS4210_CLKSEL_12M;
break;
case 48 * MHZ:
phyclk |= EXYNOS4210_CLKSEL_48M;
break;
default:
case 24 * MHZ:
phyclk |= EXYNOS4210_CLKSEL_24M;
break;
}
writel(phyclk, EXYNOS4_PHYCLK);
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
/* set clock frequency for PLL */
phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;

switch (clk_get_rate(xusbxti_clk)) {
case 9600 * KHZ:
phyclk |= EXYNOS4X12_CLKSEL_9600K;
break;
case 10 * MHZ:
phyclk |= EXYNOS4X12_CLKSEL_10M;
break;
case 12 * MHZ:
phyclk |= EXYNOS4X12_CLKSEL_12M;
break;
case 19200 * KHZ:
phyclk |= EXYNOS4X12_CLKSEL_19200K;
break;
case 20 * MHZ:
phyclk |= EXYNOS4X12_CLKSEL_20M;
break;
default:
case 24 * MHZ:
/* default reference clock */
phyclk |= EXYNOS4X12_CLKSEL_24M;
break;
}
writel(phyclk, EXYNOS4_PHYCLK);
}
clk_put(xusbxti_clk);
}

writel(phyclk, EXYNOS4_PHYCLK);
}

static int exynos4210_usb_phy0_init(struct platform_device *pdev)
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4 changes: 4 additions & 0 deletions arch/arm/plat-samsung/Kconfig
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Expand Up @@ -78,6 +78,10 @@ config S5P_HRT

# clock options

config SAMSUNG_CLOCK
bool
default y if !COMMON_CLK

config SAMSUNG_CLKSRC
bool
help
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4 changes: 2 additions & 2 deletions arch/arm/plat-samsung/Makefile
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Expand Up @@ -15,8 +15,8 @@ obj-y += init.o cpu.o
obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o
obj-$(CONFIG_S5P_HRT) += s5p-time.o

obj-y += clock.o
obj-y += pwm-clock.o
obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o
obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o

obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
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4 changes: 4 additions & 0 deletions arch/arm/plat-samsung/include/plat/cpu.h
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Expand Up @@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)

#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }

#ifndef KHZ
#define KHZ (1000)
#endif

#ifndef MHZ
#define MHZ (1000*1000)
#endif
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