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yaml
---
r: 27658
b: refs/heads/master
c: b0b0e13
h: refs/heads/master
v: v3
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Ralf Baechle committed Jun 19, 2006
1 parent 1b54869 commit 791f165
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Showing 3 changed files with 1 addition and 41 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: c583122c26ad04bb2379933dc5acc8b9479d6c67
refs/heads/master: b0b0e13e7dd309be13ab9324e67893e62b136e44
19 changes: 0 additions & 19 deletions trunk/arch/mips/mips-boards/malta/malta_smp.c
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Expand Up @@ -33,25 +33,6 @@ void core_send_ipi(int cpu, unsigned int action)
#endif /* CONFIG_MIPS_MT_SMTC */
}

/*
* Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
*/

void __init prom_build_cpu_map(void)
{
int nextslot;

/*
* As of November, 2004, MIPSsim only simulates one core
* at a time. However, that core may be a MIPS MT core
* with multiple virtual processors and thread contexts.
*/

if (read_c0_config3() & (1<<2)) {
nextslot = mipsmt_build_cpu_map(1);
}
}

/*
* Platform "CPU" startup hook
*/
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21 changes: 0 additions & 21 deletions trunk/arch/mips/mips-boards/sim/sim_smp.c
Original file line number Diff line number Diff line change
Expand Up @@ -50,27 +50,6 @@ void core_send_ipi(int cpu, unsigned int action)

}

/*
* Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
*/

void __init prom_build_cpu_map(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
int nextslot;

/*
* As of November, 2004, MIPSsim only simulates one core
* at a time. However, that core may be a MIPS MT core
* with multiple virtual processors and thread contexts.
*/

if (read_c0_config3() & (1<<2)) {
nextslot = mipsmt_build_cpu_map(1);
}
#endif /* CONFIG_MIPS_MT_SMTC */
}

/*
* Platform "CPU" startup hook
*/
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