---

yaml
---
r: 4962
b: refs/heads/master
c: cdd5186
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c5019a578f18cf3a76829626e91e5469dbd4a738
+refs/heads/master: cdd5186f753b23ab51f86679bdc4cc698ab0b893

trunk/arch/sparc64/kernel/irq.c

@@ -782,8 +782,14 @@ static void distribute_irqs(void)
 }
 #endif
 
+struct sun5_timer {
+	u64	count0;
+	u64	limit0;
+	u64	count1;
+	u64	limit1;
+};
 
-struct sun5_timer *prom_timers;
+static struct sun5_timer *prom_timers;
 static u64 prom_limit0, prom_limit1;
 
 static void map_prom_timers(void)
@@ -839,18 +845,6 @@ static void kill_prom_timer(void)
 	: "g1", "g2");
 }
 
-void enable_prom_timer(void)
-{
-	if (!prom_timers)
-		return;
-
-	/* Set it to whatever was there before. */
-	prom_timers->limit1 = prom_limit1;
-	prom_timers->count1 = 0;
-	prom_timers->limit0 = prom_limit0;
-	prom_timers->count0 = 0;
-}
-
 void init_irqwork_curcpu(void)
 {
 	register struct irq_work_struct *workp asm("o2");

trunk/include/asm-sparc64/timer.h

@@ -9,49 +9,8 @@
 
 #include <linux/types.h>
 
-/* How timers work:
- *
- * On uniprocessors we just use counter zero for the system wide
- * ticker, this performs thread scheduling, clock book keeping,
- * and runs timer based events.  Previously we used the Ultra
- * %tick interrupt for this purpose.
- *
- * On multiprocessors we pick one cpu as the master level 10 tick
- * processor.  Here this counter zero tick handles clock book
- * keeping and timer events only.  Each Ultra has it's level
- * 14 %tick interrupt set to fire off as well, even the master
- * tick cpu runs this locally.  This ticker performs thread
- * scheduling, system/user tick counting for the current thread,
- * and also profiling if enabled.
- */
-
 #include <linux/config.h>
 
-/* Two timers, traditionally steered to PIL's 10 and 14 respectively.
- * But since INO packets are used on sun5, we could use any PIL level
- * we like, however for now we use the normal ones.
- *
- * The 'reg' and 'interrupts' properties for these live in nodes named
- * 'counter-timer'.  The first of three 'reg' properties describe where
- * the sun5_timer registers are.  The other two I have no idea. (XXX)
- */
-struct sun5_timer {
-	u64	count0;
-	u64	limit0;
-	u64	count1;
-	u64	limit1;
-};
-
-#define SUN5_LIMIT_ENABLE	0x80000000
-#define SUN5_LIMIT_TOZERO	0x40000000
-#define SUN5_LIMIT_ZRESTART	0x20000000
-#define SUN5_LIMIT_CMASK	0x1fffffff
-
-/* Given a HZ value, set the limit register to so that the timer IRQ
- * gets delivered that often.
- */
-#define SUN5_HZ_TO_LIMIT(__hz)  (1000000/(__hz))
-
 struct sparc64_tick_ops {
 	void (*init_tick)(unsigned long);
 	unsigned long (*get_tick)(void);