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iwlwifi: fix rf configuration
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Johannes noticed this was completely messed up.
We got confused between masks and bit position.

Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
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Emmanuel Grumbach authored and Johannes Berg committed Jun 6, 2012
1 parent 2baa2e5 commit 7b6a2be
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Showing 2 changed files with 27 additions and 6 deletions.
17 changes: 13 additions & 4 deletions drivers/net/wireless/iwlwifi/dvm/eeprom.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1136,10 +1136,19 @@ void iwl_rf_config(struct iwl_priv *priv)

/* write radio config values to register */
if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
iwl_set_bit(priv->trans, CSR_HW_IF_CONFIG_REG,
EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
EEPROM_RF_CFG_DASH_MSK(radio_cfg));
u32 reg_val =
EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <<
CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE |
EEPROM_RF_CFG_STEP_MSK(radio_cfg) <<
CSR_HW_IF_CONFIG_REG_POS_PHY_STEP |
EEPROM_RF_CFG_DASH_MSK(radio_cfg) <<
CSR_HW_IF_CONFIG_REG_POS_PHY_DASH;

iwl_set_bits_mask(priv->trans, CSR_HW_IF_CONFIG_REG,
CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE |
CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP |
CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH, reg_val);

IWL_INFO(priv, "Radio type=0x%x-0x%x-0x%x\n",
EEPROM_RF_CFG_TYPE_MSK(radio_cfg),
EEPROM_RF_CFG_STEP_MSK(radio_cfg),
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16 changes: 14 additions & 2 deletions drivers/net/wireless/iwlwifi/iwl-csr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -155,9 +155,21 @@
#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)

/* Bits for CSR_HW_IF_CONFIG_REG */
#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
#define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
#define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
#define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
#define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)

#define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
#define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
#define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
#define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
#define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
#define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)

#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
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