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yaml
---
r: 215147
b: refs/heads/master
c: 8fa6e3d
h: refs/heads/master
i:
  215145: 08a9854
  215143: a8afb41
v: v3
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David S. Miller committed Oct 12, 2010
1 parent 96c52aa commit 7d0f4c0
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Showing 24 changed files with 13,660 additions and 13,484 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 2f34b32977ade4249601f35f7eb0cdd56b4e0f89
refs/heads/master: 8fa6e3d4549271a5b4094893f059bb95f99a8fde
101 changes: 47 additions & 54 deletions trunk/drivers/net/bnx2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -59,13 +59,13 @@
#include "bnx2_fw.h"

#define DRV_MODULE_NAME "bnx2"
#define DRV_MODULE_VERSION "2.0.17"
#define DRV_MODULE_RELDATE "July 18, 2010"
#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw"
#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j15.fw"
#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
#define DRV_MODULE_VERSION "2.0.18"
#define DRV_MODULE_RELDATE "Oct 7, 2010"
#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.0.15.fw"
#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.0.17.fw"
#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"

#define RUN_AT(x) (jiffies + (x))

Expand Down Expand Up @@ -1269,30 +1269,9 @@ bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
val |= 0x02 << 8;

if (CHIP_NUM(bp) == CHIP_NUM_5709) {
u32 lo_water, hi_water;

if (bp->flow_ctrl & FLOW_CTRL_TX)
lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
else
lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
if (lo_water >= bp->rx_ring_size)
lo_water = 0;

hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);

if (hi_water <= lo_water)
lo_water = 0;

hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
if (bp->flow_ctrl & FLOW_CTRL_TX)
val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;

if (hi_water > 0xf)
hi_water = 0xf;
else if (hi_water == 0)
lo_water = 0;
val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
}
bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
}

Expand Down Expand Up @@ -1373,8 +1352,7 @@ bnx2_set_mac_link(struct bnx2 *bp)
/* Acknowledge the interrupt. */
REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);

if (CHIP_NUM(bp) == CHIP_NUM_5709)
bnx2_init_all_rx_contexts(bp);
bnx2_init_all_rx_contexts(bp);
}

static void
Expand Down Expand Up @@ -4974,6 +4952,11 @@ bnx2_init_chip(struct bnx2 *bp)

REG_WR(bp, BNX2_HC_CONFIG, val);

if (bp->rx_ticks < 25)
bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
else
bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);

for (i = 1; i < bp->irq_nvecs; i++) {
u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
BNX2_HC_SB_CONFIG_1;
Expand Down Expand Up @@ -5242,18 +5225,20 @@ bnx2_init_all_rings(struct bnx2 *bp)
bnx2_init_rx_ring(bp, i);

if (bp->num_rx_rings > 1) {
u32 tbl_32;
u8 *tbl = (u8 *) &tbl_32;

bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
u32 tbl_32 = 0;

for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
tbl[i % 4] = i % (bp->num_rx_rings - 1);
if ((i % 4) == 3)
bnx2_reg_wr_ind(bp,
BNX2_RXP_SCRATCH_RSS_TBL + i,
cpu_to_be32(tbl_32));
int shift = (i % 8) << 2;

tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
if ((i % 8) == 7) {
REG_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
REG_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
BNX2_RLUP_RSS_COMMAND_WRITE |
BNX2_RLUP_RSS_COMMAND_HASH_MASK);
tbl_32 = 0;
}
}

val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
Expand Down Expand Up @@ -7930,16 +7915,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
goto err_out_disable;
}

/* AER (Advanced Error Reporting) hooks */
err = pci_enable_pcie_error_reporting(pdev);
if (err) {
dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
"0x%x\n", err);
/* non-fatal, continue */
}

pci_set_master(pdev);
pci_save_state(pdev);

bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
if (bp->pm_cap == 0) {
Expand Down Expand Up @@ -7994,6 +7970,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
bp->flags |= BNX2_FLAG_PCIE;
if (CHIP_REV(bp) == CHIP_REV_Ax)
bp->flags |= BNX2_FLAG_JUMBO_BROKEN;

/* AER (Advanced Error Reporting) hooks */
err = pci_enable_pcie_error_reporting(pdev);
if (err) {
dev_err(&pdev->dev, "pci_enable_pcie_error_reporting "
"failed 0x%x\n", err);
/* non-fatal, continue */
}

} else {
bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
if (bp->pcix_cap == 0) {
Expand Down Expand Up @@ -8250,16 +8235,20 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
bp->timer.data = (unsigned long) bp;
bp->timer.function = bnx2_timer;

pci_save_state(pdev);

return 0;

err_out_unmap:
if (bp->flags & BNX2_FLAG_PCIE)
pci_disable_pcie_error_reporting(pdev);

if (bp->regview) {
iounmap(bp->regview);
bp->regview = NULL;
}

err_out_release:
pci_disable_pcie_error_reporting(pdev);
pci_release_regions(pdev);

err_out_disable:
Expand Down Expand Up @@ -8449,9 +8438,10 @@ bnx2_remove_one(struct pci_dev *pdev)

kfree(bp->temp_stats_blk);

free_netdev(dev);
if (bp->flags & BNX2_FLAG_PCIE)
pci_disable_pcie_error_reporting(pdev);

pci_disable_pcie_error_reporting(pdev);
free_netdev(dev);

pci_release_regions(pdev);
pci_disable_device(pdev);
Expand Down Expand Up @@ -8565,6 +8555,9 @@ static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
}
rtnl_unlock();

if (!(bp->flags & BNX2_FLAG_PCIE))
return result;

err = pci_cleanup_aer_uncorrect_error_status(pdev);
if (err) {
dev_err(&pdev->dev,
Expand Down
17 changes: 11 additions & 6 deletions trunk/drivers/net/bnx2.h
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Original file line number Diff line number Diff line change
Expand Up @@ -352,12 +352,7 @@ struct l2_fhdr {
#define BNX2_L2CTX_BD_PRE_READ 0x00000000
#define BNX2_L2CTX_CTX_SIZE 0x00000000
#define BNX2_L2CTX_CTX_TYPE 0x00000000
#define BNX2_L2CTX_LO_WATER_MARK_DEFAULT 4
#define BNX2_L2CTX_LO_WATER_MARK_SCALE 4
#define BNX2_L2CTX_LO_WATER_MARK_DIS 0
#define BNX2_L2CTX_HI_WATER_MARK_SHIFT 4
#define BNX2_L2CTX_HI_WATER_MARK_SCALE 16
#define BNX2_L2CTX_WATER_MARKS_MSK 0x000000ff
#define BNX2_L2CTX_FLOW_CTRL_ENABLE 0x000000ff
#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
Expand Down Expand Up @@ -4185,6 +4180,15 @@ struct l2_fhdr {
#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2L<<2)
#define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3L<<2)

#define BNX2_RLUP_RSS_COMMAND 0x00002048
#define BNX2_RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR (0xfUL<<0)
#define BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK (0xffUL<<4)
#define BNX2_RLUP_RSS_COMMAND_WRITE (1UL<<12)
#define BNX2_RLUP_RSS_COMMAND_READ (1UL<<13)
#define BNX2_RLUP_RSS_COMMAND_HASH_MASK (0x7UL<<14)

#define BNX2_RLUP_RSS_DATA 0x0000204c


/*
* rbuf_reg definition
Expand Down Expand Up @@ -6077,6 +6081,7 @@ struct l2_fhdr {

#define BNX2_COM_SCRATCH 0x00120000

#define BNX2_FW_RX_LOW_LATENCY 0x00120058
#define BNX2_FW_RX_DROP_COUNT 0x00120084


Expand Down
10 changes: 5 additions & 5 deletions trunk/firmware/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -35,11 +35,11 @@ fw-shipped-$(CONFIG_ATM_AMBASSADOR) += atmsar11.fw
fw-shipped-$(CONFIG_BNX2X) += bnx2x/bnx2x-e1-6.0.34.0.fw \
bnx2x/bnx2x-e1h-6.0.34.0.fw \
bnx2x/bnx2x-e2-6.0.34.0.fw
fw-shipped-$(CONFIG_BNX2) += bnx2/bnx2-mips-09-5.0.0.j15.fw \
bnx2/bnx2-rv2p-09-5.0.0.j10.fw \
bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw \
bnx2/bnx2-mips-06-5.0.0.j6.fw \
bnx2/bnx2-rv2p-06-5.0.0.j3.fw
fw-shipped-$(CONFIG_BNX2) += bnx2/bnx2-mips-09-6.0.17.fw \
bnx2/bnx2-rv2p-09-6.0.17.fw \
bnx2/bnx2-rv2p-09ax-6.0.17.fw \
bnx2/bnx2-mips-06-6.0.15.fw \
bnx2/bnx2-rv2p-06-6.0.15.fw
fw-shipped-$(CONFIG_CASSINI) += sun/cassini.bin
fw-shipped-$(CONFIG_COMPUTONE) += intelliport2.bin
fw-shipped-$(CONFIG_CHELSIO_T3) += cxgb3/t3b_psram-1.1.0.bin \
Expand Down
11 changes: 6 additions & 5 deletions trunk/firmware/WHENCE
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Original file line number Diff line number Diff line change
Expand Up @@ -699,15 +699,16 @@ Found in hex form in kernel source.

Driver: BNX2 - Broadcom NetXtremeII

File: bnx2/bnx2-mips-06-4.6.16.fw
File: bnx2/bnx2-rv2p-06-4.6.16.fw
File: bnx2/bnx2-mips-09-4.6.17.fw
File: bnx2/bnx2-rv2p-09-4.6.15.fw
File: bnx2/bnx2-mips-06-6.0.15.fw
File: bnx2/bnx2-rv2p-06-6.0.15.fw
File: bnx2/bnx2-mips-09-6.0.17.fw
File: bnx2/bnx2-rv2p-09-6.0.17.fw
File: bnx2/bnx2-rv2p-09ax-6.0.17.fw

Licence:

This file contains firmware data derived from proprietary unpublished
source code, Copyright (c) 2004 - 2009 Broadcom Corporation.
source code, Copyright (c) 2004 - 2010 Broadcom Corporation.

Permission is hereby granted for the distribution of this firmware data
in hexadecimal or equivalent format, provided this copyright notice is
Expand Down
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