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yaml
---
r: 287569
b: refs/heads/master
c: b46c0f7
h: refs/heads/master
i:
  287567: 8832e86
v: v3
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Stephen Boyd authored and Russell King committed Feb 9, 2012
1 parent 3c35b1e commit 7e87516
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Showing 2 changed files with 7 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: b8b9987ffdc2ab9c5e2c1edad556b23ccb38249b
refs/heads/master: b46c0f74657d1fe1c1b0c1452631cc38a9e6987f
6 changes: 6 additions & 0 deletions trunk/arch/arm/mm/cache-v7.S
Original file line number Diff line number Diff line change
Expand Up @@ -54,9 +54,15 @@ loop1:
and r1, r1, #7 @ mask of the bits for current cache only
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
#ifdef CONFIG_PREEMPT
save_and_disable_irqs r9 @ make cssr&csidr read atomic
#endif
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
#ifdef CONFIG_PREEMPT
restore_irqs_notrace r9
#endif
and r2, r1, #7 @ extract the length of the cache lines
add r2, r2, #4 @ add 4 (line length offset)
ldr r4, =0x3ff
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