---

yaml --- r: 360044 b: refs/heads/master c: a264b5e h: refs/heads/master v: v3
git-mirror · Feb 16, 2013 · 7e9dc59 · 7e9dc59
1 parent 1e45681
commit 7e9dc59
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Showing 2 changed files with 13 additions and 4 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 220d9122e8c5a467fdeefc1857e077f29a623bfd
+refs/heads/master: a264b5e8dc3cae1b07cea010d6283be6e67b0209
diff --git a/trunk/arch/mips/pci/pci-xlp.c b/trunk/arch/mips/pci/pci-xlp.c
@@ -191,7 +191,13 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 	return 0;
 }
 
-static int xlp_enable_pci_bswap(void)
+/*
+ * If big-endian, enable hardware byteswap on the PCIe bridges.
+ * This will make both the SoC and PCIe devices behave consistently with
+ * readl/writel.
+ */
+#ifdef __BIG_ENDIAN
+static void xlp_config_pci_bswap(void)
 {
 	uint64_t pciebase, sysbase;
 	int node, i;
@@ -222,8 +228,11 @@ static int xlp_enable_pci_bswap(void)
 		reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
 		nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
 	}
-	return 0;
 }
+#else
+/* Swap configuration not needed in little-endian mode */
+static inline void xlp_config_pci_bswap(void) {}
+#endif /* __BIG_ENDIAN */
 
 static int __init pcibios_init(void)
 {
@@ -235,7 +244,7 @@ static int __init pcibios_init(void)
 	ioport_resource.start =  0;
 	ioport_resource.end   = ~0;
 
-	xlp_enable_pci_bswap();
+	xlp_config_pci_bswap();
 	set_io_port_base(CKSEG1);
 	nlm_pci_controller.io_map_base = CKSEG1;