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yaml
---
r: 247720
b: refs/heads/master
c: 1ff30a5
h: refs/heads/master
v: v3
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Matt Carlson authored and David S. Miller committed May 19, 2011
1 parent 7e2e758 commit 8041c75
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Showing 3 changed files with 21 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 432aa7ed75b3adaef6040d2cbe745fdd1c899415
refs/heads/master: 1ff30a59f6d0c754e99442501a5145bdbbcfa6ea
16 changes: 16 additions & 0 deletions trunk/drivers/net/tg3.c
Original file line number Diff line number Diff line change
Expand Up @@ -7990,6 +7990,22 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
tw32(GRC_MODE, grc_mode);
}

if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
u32 grc_mode = tr32(GRC_MODE);

/* Access the lower 1K of DL PCIE block registers. */
val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);

val = tr32(TG3_PCIE_TLDLPL_PORT +
TG3_PCIE_DL_LO_FTSMAX);
val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
val | TG3_PCIE_DL_LO_FTSMAX_VAL);

tw32(GRC_MODE, grc_mode);
}

val = tr32(TG3_CPMU_LSPD_10MB_CLK);
val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
val |= CPMU_LSPD_10MB_MACCLK_6_25;
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4 changes: 4 additions & 0 deletions trunk/drivers/net/tg3.h
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Expand Up @@ -180,6 +180,7 @@
#define CHIPREV_5750_BX 0x41
#define CHIPREV_5784_AX 0x57840
#define CHIPREV_5761_AX 0x57610
#define CHIPREV_57765_AX 0x577650
#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
#define METAL_REV_A0 0x00
#define METAL_REV_A1 0x01
Expand Down Expand Up @@ -1951,6 +1952,9 @@

/* Alternate PCIE definitions */
#define TG3_PCIE_TLDLPL_PORT 0x00007c00
#define TG3_PCIE_DL_LO_FTSMAX 0x0000000c
#define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff
#define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
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