---

yaml
---
r: 31859
b: refs/heads/master
c: 7c6efda
h: refs/heads/master
i:
  31857: cbe2072
  31855: a1d09e2
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 980a65136569b841cebaad524a34482b0b1627a9
+refs/heads/master: 7c6efda5996c26c468eaba178af9bac8b70dbdcb

trunk/arch/powerpc/kernel/legacy_serial.c

@@ -126,6 +126,8 @@ static int __init add_legacy_soc_port(struct device_node *np,
 		return -1;
 
 	addr = of_translate_address(soc_dev, addrp);
+	if (addr == OF_BAD_ADDR)
+		return -1;
 
 	/* Add port, irq will be dealt with later. We passed a translated
 	 * IO port value. It will be fixed up later along with the irq
@@ -141,6 +143,8 @@ static int __init add_legacy_isa_port(struct device_node *np,
 	int index = -1;
 	phys_addr_t taddr;
 
+	DBG(" -> add_legacy_isa_port(%s)\n", np->full_name);
+
 	/* Get the ISA port number */
 	reg = (u32 *)get_property(np, "reg", NULL);
 	if (reg == NULL)
@@ -161,9 +165,12 @@ static int __init add_legacy_isa_port(struct device_node *np,
 
 	/* Translate ISA address */
 	taddr = of_translate_address(np, reg);
+	if (taddr == OF_BAD_ADDR)
+		return -1;
 
 	/* Add port, irq will be dealt with later */
-	return add_legacy_port(np, index, UPIO_PORT, reg[1], taddr, NO_IRQ, UPF_BOOT_AUTOCONF);
+	return add_legacy_port(np, index, UPIO_PORT, reg[1], taddr,
+			       NO_IRQ, UPF_BOOT_AUTOCONF);
 
 }
 
@@ -176,6 +183,8 @@ static int __init add_legacy_pci_port(struct device_node *np,
 	unsigned int flags;
 	int iotype, index = -1, lindex = 0;
 
+	DBG(" -> add_legacy_pci_port(%s)\n", np->full_name);
+
 	/* We only support ports that have a clock frequency properly
 	 * encoded in the device-tree (that is have an fcode). Anything
 	 * else can't be used that early and will be normally probed by
@@ -194,6 +203,8 @@ static int __init add_legacy_pci_port(struct device_node *np,
 	/* We only support BAR 0 for now */
 	iotype = (flags & IORESOURCE_MEM) ? UPIO_MEM : UPIO_PORT;
 	addr = of_translate_address(pci_dev, addrp);
+	if (addr == OF_BAD_ADDR)
+		return -1;
 
 	/* Set the IO base to the same as the translated address for MMIO,
 	 * or to the domain local IO base for PIO (it will be fixed up later)