---

yaml --- r: 205818 b: refs/heads/master c: 4574fae h: refs/heads/master v: v3
git-mirror · Jul 8, 2010 · 81e416a · 81e416a
1 parent 08b01e7
commit 81e416a
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Showing 4 changed files with 10 additions and 9 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ec528652a92e18975bb6fe3e2f4f8f927b71ec88
+refs/heads/master: 4574fae58d840d78e44ae33236899f92bfb6b4a9
diff --git a/trunk/drivers/staging/tidspbridge/core/tiomap3430.c b/trunk/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -73,8 +73,6 @@
 #define PAGES_II_LVL_TABLE   512
 #define PHYS_TO_PAGE(phys)      pfn_to_page((phys) >> PAGE_SHIFT)
 
-#define MMU_GFLUSH 0x60
-
 /* Forward Declarations: */
 static int bridge_brd_monitor(struct bridge_dev_context *dev_context);
 static int bridge_brd_read(struct bridge_dev_context *dev_context,
@@ -218,18 +216,13 @@ static struct bridge_drv_interface drv_interface_fxns = {
 	bridge_msg_set_queue_id,
 };
 
-static inline void tlb_flush_all(const void __iomem *base)
-{
-	__raw_writeb(__raw_readb(base + MMU_GFLUSH) | 1, base + MMU_GFLUSH);
-}
-
 static inline void flush_all(struct bridge_dev_context *dev_context)
 {
 	if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||
 	    dev_context->dw_brd_state == BRD_HIBERNATION)
 		wake_dsp(dev_context, NULL);
 
-	tlb_flush_all(dev_context->dw_dsp_mmu_base);
+	hw_mmu_tlb_flush_all(dev_context->dw_dsp_mmu_base);
 }
 
 static void bad_page_dump(u32 pa, struct page *pg)

diff --git a/trunk/drivers/staging/tidspbridge/hw/hw_mmu.c b/trunk/drivers/staging/tidspbridge/hw/hw_mmu.c
@@ -35,6 +35,7 @@
 #define MMU_SMALL_PAGE_MASK      0xFFFFF000
 
 #define MMU_LOAD_TLB	0x00000001
+#define MMU_GFLUSH	0x60
 
 /*
  * hw_mmu_page_size_t: Enumerated Type used to specify the MMU Page Size(SLSS)
@@ -585,3 +586,8 @@ static hw_status mmu_set_ram_entry(const void __iomem *baseAddress,
 	return status;
 
 }
+
+void hw_mmu_tlb_flush_all(const void __iomem *base)
+{
+	__raw_writeb(1, base + MMU_GFLUSH);
+}
diff --git a/trunk/drivers/staging/tidspbridge/hw/hw_mmu.h b/trunk/drivers/staging/tidspbridge/hw/hw_mmu.h
@@ -97,6 +97,8 @@ extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
 extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va,
 				  u32 page_size, u32 virtualAddr);
 
+void hw_mmu_tlb_flush_all(const void __iomem *base);
+
 static inline u32 hw_mmu_pte_addr_l1(u32 L1_base, u32 va)
 {
 	u32 pte_addr;