---

yaml
---
r: 311531
b: refs/heads/master
c: 86f887c
h: refs/heads/master
i:
  311529: cf65967
  311527: 49adbec
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c207d2df1c1b2a160b7d52229e5a43feea6a7d26
+refs/heads/master: 86f887c105b909a2cea7b06f2136d66b3438b038

trunk/arch/arm/mach-shmobile/intc-r8a7779.c

@@ -35,6 +35,9 @@
 #define INT2SMSKCR3 0xfe7822ac
 #define INT2SMSKCR4 0xfe7822b0
 
+#define INT2NTSR0 0xfe700060
+#define INT2NTSR1 0xfe700064
+
 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 {
 	return 0; /* always allow wakeup */
@@ -49,6 +52,10 @@ void __init r8a7779_init_irq(void)
 	gic_init(0, 29, gic_dist_base, gic_cpu_base);
 	gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 
+	/* route all interrupts to ARM */
+	__raw_writel(0xffffffff, INT2NTSR0);
+	__raw_writel(0x3fffffff, INT2NTSR1);
+
 	/* unmask all known interrupts in INTCS2 */
 	__raw_writel(0xfffffff0, INT2SMSKCR0);
 	__raw_writel(0xfff7ffff, INT2SMSKCR1);