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yaml
---
r: 242540
b: refs/heads/master
c: 27e5c5a
h: refs/heads/master
v: v3
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Thomas Gleixner committed Mar 24, 2011
1 parent 5002cb3 commit 8278005
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Showing 9 changed files with 76 additions and 76 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 9f7b21871355d00ea0aa4dc84e44f81d90a53f55
refs/heads/master: 27e5c5a9a240d2a7790bfe31045020a043c5d74a
8 changes: 4 additions & 4 deletions trunk/arch/m32r/platforms/m32104ut/setup.c
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Original file line number Diff line number Diff line change
Expand Up @@ -76,28 +76,28 @@ void __init init_IRQ(void)

#if defined(CONFIG_SMC91X)
/* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
handle_level_irq);
/* "H" level sense */
cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11;
disable_m32104ut_irq(M32R_IRQ_INT0);
#endif /* CONFIG_SMC91X */

/* MFT2 : system timer */
set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_m32104ut_irq(M32R_IRQ_MFT2);

#ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */
set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
disable_m32104ut_irq(M32R_IRQ_SIO0_R);

/* SIO0_S : uart send data */
set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
disable_m32104ut_irq(M32R_IRQ_SIO0_S);
Expand Down
28 changes: 14 additions & 14 deletions trunk/arch/m32r/platforms/m32700ut/setup.c
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Original file line number Diff line number Diff line change
Expand Up @@ -259,76 +259,76 @@ void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN,
irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN,
&m32700ut_lanpld_irq_type, handle_level_irq);
lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
#endif /* CONFIG_SMC91X */

/* MFT2 : system timer */
set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_m32700ut_irq(M32R_IRQ_MFT2);

/* SIO0 : receive */
set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_SIO0_R);

/* SIO0 : send */
set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_SIO0_S);

/* SIO1 : receive */
set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_SIO1_R);

/* SIO1 : send */
set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_SIO1_S);

/* DMA1 : */
set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_DMA1].icucr = 0;
disable_m32700ut_irq(M32R_IRQ_DMA1);

#ifdef CONFIG_SERIAL_M32R_PLDSIO
/* INT#1: SIO0 Receive on PLD */
set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);

/* INT#1: SIO0 Send on PLD */
set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
#endif /* CONFIG_SERIAL_M32R_PLDSIO */

/* INT#1: CFC IREQ on PLD */
set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);

/* INT#1: CFC Insert on PLD */
set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);

/* INT#1: CFC Eject on PLD */
set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
Expand All @@ -349,7 +349,7 @@ void __init init_IRQ(void)

#if defined(CONFIG_USB)
outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
&m32700ut_lcdpld_irq_type, handle_level_irq);

lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
Expand All @@ -366,7 +366,7 @@ void __init init_IRQ(void)
/*
* INT3# is used for AR
*/
set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_m32700ut_irq(M32R_IRQ_INT3);
Expand Down
16 changes: 8 additions & 8 deletions trunk/arch/m32r/platforms/mappi/setup.c
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Original file line number Diff line number Diff line change
Expand Up @@ -75,53 +75,53 @@ void __init init_IRQ(void)

#ifdef CONFIG_NE2000
/* INT0 : LAN controller (RTL8019AS) */
set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
disable_mappi_irq(M32R_IRQ_INT0);
#endif /* CONFIG_M32R_NE2000 */

/* MFT2 : system timer */
set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_mappi_irq(M32R_IRQ_MFT2);

#ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */
set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO0_R);

/* SIO0_S : uart send data */
set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO0_S);

/* SIO1_R : uart receive data */
set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO1_R);

/* SIO1_S : uart send data */
set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_SERIAL_M32R_SIO */

#if defined(CONFIG_M32R_PCC)
/* INT1 : pccard0 interrupt */
set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
disable_mappi_irq(M32R_IRQ_INT1);

/* INT2 : pccard1 interrupt */
set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
disable_mappi_irq(M32R_IRQ_INT2);
Expand Down
20 changes: 10 additions & 10 deletions trunk/arch/m32r/platforms/mappi2/setup.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -76,66 +76,66 @@ void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
/* INT0 : LAN controller (SMC91111) */
set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_mappi2_irq(M32R_IRQ_INT0);
#endif /* CONFIG_SMC91X */

/* MFT2 : system timer */
set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_mappi2_irq(M32R_IRQ_MFT2);

#ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */
set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_mappi2_irq(M32R_IRQ_SIO0_R);

/* SIO0_S : uart send data */
set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_mappi2_irq(M32R_IRQ_SIO0_S);
/* SIO1_R : uart receive data */
set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_mappi2_irq(M32R_IRQ_SIO1_R);

/* SIO1_S : uart send data */
set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_mappi2_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_M32R_USE_DBG_CONSOLE */

#if defined(CONFIG_USB)
/* INT1 : USB Host controller interrupt */
set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
disable_mappi2_irq(M32R_IRQ_INT1);
#endif /* CONFIG_USB */

/* ICUCR40: CFC IREQ */
set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
handle_level_irq);
icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
disable_mappi2_irq(PLD_IRQ_CFIREQ);

#if defined(CONFIG_M32R_CFC)
/* ICUCR41: CFC Insert */
set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
handle_level_irq);
icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
disable_mappi2_irq(PLD_IRQ_CFC_INSERT);

/* ICUCR42: CFC Eject */
set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
handle_level_irq);
icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
Expand Down
20 changes: 10 additions & 10 deletions trunk/arch/m32r/platforms/mappi3/setup.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -75,68 +75,68 @@ void __init init_IRQ(void)
{
#if defined(CONFIG_SMC91X)
/* INT0 : LAN controller (SMC91111) */
set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_mappi3_irq(M32R_IRQ_INT0);
#endif /* CONFIG_SMC91X */

/* MFT2 : system timer */
set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_mappi3_irq(M32R_IRQ_MFT2);

#ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */
set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_mappi3_irq(M32R_IRQ_SIO0_R);

/* SIO0_S : uart send data */
set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_mappi3_irq(M32R_IRQ_SIO0_S);
/* SIO1_R : uart receive data */
set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_mappi3_irq(M32R_IRQ_SIO1_R);

/* SIO1_S : uart send data */
set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_mappi3_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_M32R_USE_DBG_CONSOLE */

#if defined(CONFIG_USB)
/* INT1 : USB Host controller interrupt */
set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
handle_level_irq);
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
disable_mappi3_irq(M32R_IRQ_INT1);
#endif /* CONFIG_USB */

/* CFC IREQ */
set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
handle_level_irq);
icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
disable_mappi3_irq(PLD_IRQ_CFIREQ);

#if defined(CONFIG_M32R_CFC)
/* ICUCR41: CFC Insert & eject */
set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
handle_level_irq);
icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
disable_mappi3_irq(PLD_IRQ_CFC_INSERT);

#endif /* CONFIG_M32R_CFC */

/* IDE IREQ */
set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
handle_level_irq);
icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_mappi3_irq(PLD_IRQ_IDEIREQ);
Expand Down
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