---

yaml
---
r: 377471
b: refs/heads/master
c: 1abd601
h: refs/heads/master
i:
  377469: 4894845
  377467: 147e18d
  377463: d7a786b
  377455: b2929ce
  377439: fa6c1de
  377407: f87ef06
  377343: a291cd0
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 8d5bc1a6ac40885078bbb0552b4283a3e58c462e
+refs/heads/master: 1abd601864f42a5d10e6fa0b66582591b4497b94

trunk/Documentation/networking/ip-sysctl.txt

@@ -420,10 +420,10 @@ tcp_synack_retries - INTEGER
 	for a passive TCP connection will happen after 63seconds.
 
 tcp_syncookies - BOOLEAN
-	Only valid when the kernel was compiled with CONFIG_SYN_COOKIES
+	Only valid when the kernel was compiled with CONFIG_SYNCOOKIES
 	Send out syncookies when the syn backlog queue of a socket
 	overflows. This is to prevent against the common 'SYN flood attack'
-	Default: 1
+	Default: FALSE
 
 	Note, that syncookies is fallback facility.
 	It MUST NOT be used to help highly loaded servers to stand

trunk/Makefile

@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 10
 SUBLEVEL = 0
-EXTRAVERSION = -rc7
+EXTRAVERSION = -rc6
 NAME = Unicycling Gorilla
 
 # *DOCUMENTATION*

trunk/arch/arm/Kconfig

@@ -1087,20 +1087,6 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
-config PJ4B_ERRATA_4742
-	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
-	depends on CPU_PJ4B && MACH_ARMADA_370
-	default y
-	help
-	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
-	  Event (WFE) IDLE states, a specific timing sensitivity exists between
-	  the retiring WFI/WFE instructions and the newly issued subsequent
-	  instructions.  This sensitivity can result in a CPU hang scenario.
-	  Workaround:
-	  The software must insert either a Data Synchronization Barrier (DSB)
-	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
-	  instruction
-
 config ARM_ERRATA_326103
 	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 	depends on CPU_V6
@@ -1203,16 +1189,6 @@ config PL310_ERRATA_588369
 	   is not correctly implemented in PL310 as clean lines are not
 	   invalidated as a result of these operations.
 
-config ARM_ERRATA_643719
-	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
-	depends on CPU_V7 && SMP
-	help
-	  This option enables the workaround for the 643719 Cortex-A9 (prior to
-	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
-	  register returns zero when it should return one. The workaround
-	  corrects this value, ensuring cache maintenance operations which use
-	  it behave as intended and avoiding data corruption.
-
 config ARM_ERRATA_720789
 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
 	depends on CPU_V7
@@ -2030,7 +2006,7 @@ config XIP_PHYS_ADDR
 
 config KEXEC
 	bool "Kexec system call (EXPERIMENTAL)"
-	depends on (!SMP || PM_SLEEP_SMP)
+	depends on (!SMP || HOTPLUG_CPU)
 	help
 	  kexec is a system call that implements the ability to shutdown your
 	  current kernel, and to start another kernel.  It is like a reboot

trunk/arch/arm/boot/compressed/Makefile

@@ -116,8 +116,7 @@ targets       := vmlinux vmlinux.lds \
 
 # Make sure files are removed during clean
 extra-y       += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern \
-		 lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) \
-		 hyp-stub.S
+		 lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs)
 
 ifeq ($(CONFIG_FUNCTION_TRACER),y)
 ORIG_CFLAGS := $(KBUILD_CFLAGS)

trunk/arch/arm/boot/dts/exynos5250-pinctrl.dtsi

@@ -763,7 +763,7 @@
 		};
 	};
 
-	pinctrl@03860000 {
+	pinctrl@03680000 {
 		gpz: gpz {
 			gpio-controller;
 			#gpio-cells = <2>;

trunk/arch/arm/boot/dts/exynos5250.dtsi

@@ -161,9 +161,9 @@
 		interrupts = <0 50 0>;
 	};
 
-	pinctrl_3: pinctrl@03860000 {
+	pinctrl_3: pinctrl@03680000 {
 		compatible = "samsung,exynos5250-pinctrl";
-		reg = <0x03860000 0x1000>;
+		reg = <0x0368000 0x1000>;
 		interrupts = <0 47 0>;
 	};
 

trunk/arch/arm/include/asm/cacheflush.h

@@ -320,7 +320,9 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 }
 
 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
-extern void flush_kernel_dcache_page(struct page *);
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+}
 
 #define flush_dcache_mmap_lock(mapping) \
 	spin_lock_irq(&(mapping)->tree_lock)

trunk/arch/arm/include/asm/cputype.h

@@ -32,8 +32,6 @@
 
 #define MPIDR_HWID_BITMASK 0xFFFFFF
 
-#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
-
 #define MPIDR_LEVEL_BITS 8
 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
 

trunk/arch/arm/include/asm/glue-proc.h

@@ -230,15 +230,6 @@
 # endif
 #endif
 
-#ifdef CONFIG_CPU_PJ4B
-# ifdef CPU_NAME
-#  undef  MULTI_CPU
-#  define MULTI_CPU
-# else
-#  define CPU_NAME cpu_pj4b
-# endif
-#endif
-
 #ifndef MULTI_CPU
 #define cpu_proc_init			__glue(CPU_NAME,_proc_init)
 #define cpu_proc_fin			__glue(CPU_NAME,_proc_fin)

trunk/arch/arm/include/asm/smp_plat.h

@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
 /*
  * Logical CPU mapping.
  */
-extern u32 __cpu_logical_map[];
+extern int __cpu_logical_map[];
 #define cpu_logical_map(cpu)	__cpu_logical_map[cpu]
 /*
  * Retrieve logical cpu index corresponding to a given MPIDR[23:0]

trunk/arch/arm/kernel/devtree.c

@@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
 	u32 i, j, cpuidx = 1;
 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
+	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
 	bool bootcpu_valid = false;
 	cpus = of_find_node_by_path("/cpus");
 
@@ -92,9 +92,6 @@ void __init arm_dt_init_cpu_maps(void)
 	for_each_child_of_node(cpus, cpu) {
 		u32 hwid;
 
-		if (of_node_cmp(cpu->type, "cpu"))
-			continue;
-
 		pr_debug(" * %s...\n", cpu->full_name);
 		/*
 		 * A device tree containing CPU nodes with missing "reg"
@@ -152,10 +149,9 @@ void __init arm_dt_init_cpu_maps(void)
 		tmp_map[i] = hwid;
 	}
 
-	if (!bootcpu_valid) {
-		pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
+	if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
+				 "fall back to default cpu_logical_map\n"))
 		return;
-	}
 
 	/*
 	 * Since the boot CPU node contains proper data, and all nodes have

trunk/arch/arm/kernel/machine_kexec.c

@@ -134,10 +134,6 @@ void machine_kexec(struct kimage *image)
 	unsigned long reboot_code_buffer_phys;
 	void *reboot_code_buffer;
 
-	if (num_online_cpus() > 1) {
-		pr_err("kexec: error: multiple CPUs still online\n");
-		return;
-	}
 
 	page_list = image->head & PAGE_MASK;
 

trunk/arch/arm/kernel/process.c

@@ -184,61 +184,30 @@ int __init reboot_setup(char *str)
 
 __setup("reboot=", reboot_setup);
 
-/*
- * Called by kexec, immediately prior to machine_kexec().
- *
- * This must completely disable all secondary CPUs; simply causing those CPUs
- * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
- * kexec'd kernel to use any and all RAM as it sees fit, without having to
- * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
- * functionality embodied in disable_nonboot_cpus() to achieve this.
- */
 void machine_shutdown(void)
 {
-	disable_nonboot_cpus();
+#ifdef CONFIG_SMP
+	smp_send_stop();
+#endif
 }
 
-/*
- * Halting simply requires that the secondary CPUs stop performing any
- * activity (executing tasks, handling interrupts). smp_send_stop()
- * achieves this.
- */
 void machine_halt(void)
 {
-	smp_send_stop();
-
+	machine_shutdown();
 	local_irq_disable();
 	while (1);
 }
 
-/*
- * Power-off simply requires that the secondary CPUs stop performing any
- * activity (executing tasks, handling interrupts). smp_send_stop()
- * achieves this. When the system power is turned off, it will take all CPUs
- * with it.
- */
 void machine_power_off(void)
 {
-	smp_send_stop();
-
+	machine_shutdown();
 	if (pm_power_off)
 		pm_power_off();
 }
 
-/*
- * Restart requires that the secondary CPUs stop performing any activity
- * while the primary CPU resets the system. Systems with a single CPU can
- * use soft_restart() as their machine descriptor's .restart hook, since that
- * will cause the only available CPU to reset. Systems with multiple CPUs must
- * provide a HW restart implementation, to ensure that all CPUs reset at once.
- * This is required so that any code running after reset on the primary CPU
- * doesn't have to co-ordinate with other CPUs to ensure they aren't still
- * executing pre-reset code, and using RAM that the primary CPU's code wishes
- * to use. Implementing such co-ordination would be essentially impossible.
- */
 void machine_restart(char *cmd)
 {
-	smp_send_stop();
+	machine_shutdown();
 
 	arm_pm_restart(reboot_mode, cmd);
 

trunk/arch/arm/kernel/setup.c

@@ -444,7 +444,7 @@ void notrace cpu_init(void)
 	    : "r14");
 }
 
-u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
+int __cpu_logical_map[NR_CPUS];
 
 void __init smp_setup_processor_id(void)
 {

trunk/arch/arm/kernel/smp.c

@@ -651,6 +651,17 @@ void smp_send_reschedule(int cpu)
 	smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static void smp_kill_cpus(cpumask_t *mask)
+{
+	unsigned int cpu;
+	for_each_cpu(cpu, mask)
+		platform_cpu_kill(cpu);
+}
+#else
+static void smp_kill_cpus(cpumask_t *mask) { }
+#endif
+
 void smp_send_stop(void)
 {
 	unsigned long timeout;
@@ -668,6 +679,8 @@ void smp_send_stop(void)
 
 	if (num_online_cpus() > 1)
 		pr_warning("SMP: failed to stop secondary CPUs\n");
+
+	smp_kill_cpus(&mask);
 }
 
 /*

trunk/arch/arm/mm/cache-v7.S

@@ -92,14 +92,6 @@ ENTRY(v7_flush_dcache_louis)
 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr, r0 = clidr
 	ALT_SMP(ands	r3, r0, #(7 << 21))	@ extract LoUIS from clidr
 	ALT_UP(ands	r3, r0, #(7 << 27))	@ extract LoUU from clidr
-#ifdef CONFIG_ARM_ERRATA_643719
-	ALT_SMP(mrceq	p15, 0, r2, c0, c0, 0)	@ read main ID register
-	ALT_UP(moveq	pc, lr)			@ LoUU is zero, so nothing to do
-	ldreq	r1, =0x410fc090                 @ ID of ARM Cortex A9 r0p?
-	biceq	r2, r2, #0x0000000f             @ clear minor revision number
-	teqeq	r2, r1                          @ test for errata affected core and if so...
-	orreqs	r3, #(1 << 21)			@   fix LoUIS value (and set flags state to 'ne')
-#endif
 	ALT_SMP(mov	r3, r3, lsr #20)	@ r3 = LoUIS * 2
 	ALT_UP(mov	r3, r3, lsr #26)	@ r3 = LoUU * 2
 	moveq	pc, lr				@ return if level == 0

trunk/arch/arm/mm/flush.c

@@ -300,39 +300,6 @@ void flush_dcache_page(struct page *page)
 }
 EXPORT_SYMBOL(flush_dcache_page);
 
-/*
- * Ensure cache coherency for the kernel mapping of this page. We can
- * assume that the page is pinned via kmap.
- *
- * If the page only exists in the page cache and there are no user
- * space mappings, this is a no-op since the page was already marked
- * dirty at creation.  Otherwise, we need to flush the dirty kernel
- * cache lines directly.
- */
-void flush_kernel_dcache_page(struct page *page)
-{
-	if (cache_is_vivt() || cache_is_vipt_aliasing()) {
-		struct address_space *mapping;
-
-		mapping = page_mapping(page);
-
-		if (!mapping || mapping_mapped(mapping)) {
-			void *addr;
-
-			addr = page_address(page);
-			/*
-			 * kmap_atomic() doesn't set the page virtual
-			 * address for highmem pages, and
-			 * kunmap_atomic() takes care of cache
-			 * flushing already.
-			 */
-			if (!IS_ENABLED(CONFIG_HIGHMEM) || addr)
-				__cpuc_flush_dcache_area(addr, PAGE_SIZE);
-		}
-	}
-}
-EXPORT_SYMBOL(flush_kernel_dcache_page);
-
 /*
  * Flush an anonymous page so that users of get_user_pages()
  * can safely access the data.  The expected sequence is:

trunk/arch/arm/mm/mmu.c

@@ -616,12 +616,10 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 	} while (pte++, addr += PAGE_SIZE, addr != end);
 }
 
-static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
+static void __init map_init_section(pmd_t *pmd, unsigned long addr,
 			unsigned long end, phys_addr_t phys,
 			const struct mem_type *type)
 {
-	pmd_t *p = pmd;
-
 #ifndef CONFIG_ARM_LPAE
 	/*
 	 * In classic MMU format, puds and pmds are folded in to
@@ -640,7 +638,7 @@ static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
 		phys += SECTION_SIZE;
 	} while (pmd++, addr += SECTION_SIZE, addr != end);
 
-	flush_pmd_entry(p);
+	flush_pmd_entry(pmd);
 }
 
 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
@@ -663,7 +661,7 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 		 */
 		if (type->prot_sect &&
 				((addr | next | phys) & ~SECTION_MASK) == 0) {
-			__map_init_section(pmd, addr, next, phys, type);
+			map_init_section(pmd, addr, next, phys, type);
 		} else {
 			alloc_init_pte(pmd, addr, next,
 						__phys_to_pfn(phys), type);

trunk/arch/arm/mm/nommu.c

@@ -57,12 +57,6 @@ void flush_dcache_page(struct page *page)
 }
 EXPORT_SYMBOL(flush_dcache_page);
 
-void flush_kernel_dcache_page(struct page *page)
-{
-	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
-}
-EXPORT_SYMBOL(flush_kernel_dcache_page);
-
 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 		       unsigned long uaddr, void *dst, const void *src,
 		       unsigned long len)