---

yaml
---
r: 344337
b: refs/heads/master
c: 3ee11ae
h: refs/heads/master
i:
  344335: 147f5c8
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 2f96fbb7d851740d0594a6b74142083d51483ab5
+refs/heads/master: 3ee11aef75db51c69cb8cb91dd01afb28036f1b5

trunk/Documentation/devicetree/bindings/arm/l2cc.txt

@@ -10,6 +10,12 @@ Required properties:
 	"arm,pl310-cache"
 	"arm,l220-cache"
 	"arm,l210-cache"
+	"marvell,aurora-system-cache": Marvell Controller designed to be
+     compatible with the ARM one, with system cache mode (meaning
+     maintenance operations on L1 are broadcasted to the L2 and L2
+     performs the same operation).
+	"marvell,"aurora-outer-cache: Marvell Controller designed to be
+	 compatible with the ARM one with outer cache mode.
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
@@ -29,6 +35,9 @@ Optional properties:
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
 - interrupts : 1 combined interrupt.
+- cache-id-part: cache id part number to be used if it is not present
+  on hardware
+- wt-override: If present then L2 is forced to Write through mode
 
 Example: