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yaml
---
r: 68086
b: refs/heads/master
c: e923090
h: refs/heads/master
v: v3
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Albert Lee authored and Jeff Garzik committed Oct 12, 2007
1 parent c39c11a commit 8399f93
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Showing 2 changed files with 1 addition and 6 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: c7293870a93a99e9ce0f4d98f3a271539c7c6ad6
refs/heads/master: e923090ddd9fef1d4e06dc6c5295e29baced19f3
5 changes: 0 additions & 5 deletions trunk/drivers/ata/pata_pdc2027x.c
Original file line number Diff line number Diff line change
Expand Up @@ -561,12 +561,10 @@ static long pdc_read_counter(struct ata_host *host)
retry:
bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
rmb();

/* Read the counter values again for verification */
bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
rmb();

counter = (bccrh << 15) | bccrl;

Expand Down Expand Up @@ -741,9 +739,6 @@ static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
*/
pll_clock = pdc_detect_pll_input_clock(host);

if (pll_clock < 0) /* counter overflow? Try again. */
pll_clock = pdc_detect_pll_input_clock(host);

dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);

/* Adjust PLL control register */
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