---

yaml --- r: 292447 b: refs/heads/master c: ed8a279 h: refs/heads/master i: 292445: 972c50f 292443: 2b30685 292439: fe259d3 292431: 41db8a9 292415: 63ca223 v: v3
git-mirror · Mar 4, 2012 · 83f61b5 · 83f61b5
1 parent ba49b61
commit 83f61b5
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Showing 4 changed files with 17 additions and 14 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3b2039b26619745a736b896caf8df05a2a15df3a
+refs/heads/master: ed8a2798f6cff0dc68ca7d5800279525aa310fd0
diff --git a/trunk/arch/m68k/include/asm/m532xsim.h b/trunk/arch/m68k/include/asm/m532xsim.h
@@ -36,6 +36,8 @@
 #define MCF_IRQ_FECTX0	    (MCFINT_VECBASE + MCFINT_FECTX0)
 #define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)
 
+#define	MCF_IRQ_QSPI	    (MCFINT_VECBASE + MCFINT_QSPI)
+
 #define MCF_WTM_WCR	MCF_REG16(0xFC098000)
 
 /*
@@ -103,6 +105,16 @@
 #define	MCFFEC_BASE0		0xFC030000	/* Base address of FEC0 */
 #define	MCFFEC_SIZE0		0x800		/* Size of FEC0 region */
 
+/*
+ *  QSPI module.
+ */
+#define	MCFQSPI_BASE		0xFC058000	/* Base address of QSPI */
+#define	MCFQSPI_SIZE		0x40		/* Size of QSPI region */
+
+#define	MCFQSPI_CS0		84
+#define	MCFQSPI_CS1		85
+#define	MCFQSPI_CS2		86
+
 /*
  *  Timer module.
  */

diff --git a/trunk/arch/m68k/include/asm/mcfqspi.h b/trunk/arch/m68k/include/asm/mcfqspi.h
@@ -21,11 +21,6 @@
 #ifndef mcfqspi_h
 #define mcfqspi_h
 
-#if defined(CONFIG_M532x)
-#define MCFQSPI_IOBASE         0xFC058000
-#endif
-#define MCFQSPI_IOSIZE		0x40
-
 /**
  * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
  * @setup: setup the control; allocate gpio's, etc. May be NULL.

diff --git a/trunk/arch/m68k/platform/532x/config.c b/trunk/arch/m68k/platform/532x/config.c
@@ -36,21 +36,17 @@
 #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
 static struct resource m532x_qspi_resources[] = {
 	{
-		.start		= MCFQSPI_IOBASE,
-		.end		= MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
+		.start		= MCFQSPI_BASE,
+		.end		= MCFQSPI_BASE + MCFQSPI_SIZE - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 	{
-		.start		= MCFINT_VECBASE + MCFINT_QSPI,
-		.end		= MCFINT_VECBASE + MCFINT_QSPI,
+		.start		= MCF_IRQ_QSPI,
+		.end		= MCF_IRQ_QSPI,
 		.flags		= IORESOURCE_IRQ,
 	},
 };
 
-#define MCFQSPI_CS0    84
-#define MCFQSPI_CS1    85
-#define MCFQSPI_CS2    86
-
 static int m532x_cs_setup(struct mcfqspi_cs_control *cs_control)
 {
 	int status;